A Power-Constrained MPU Roadmap for International Technology Roadmap for Semiconductors

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A Power-Constrained MPU Roadmap for
International Technology Roadmap for
Semiconductors

• Kwangok Jeong and Andrew B. Kahng
• UCSD VLSI CAD Laboratory
• abk_at_cs.ucsd.edu
• CSE and ECE Department
• University of California, San Diego

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Needs for MPU Roadmap

• What is the limit of future SoC designs?
• MPU uses highest frequency / power / integration
  level of a technology
• ? MPU is a reference of leading edge SoC designs
• For a good MPU roadmap,
• How would you approach the task of roadmapping
  MPU?
• On what technology parameters should the MPU
  roadmap depend?
• What constraints cause fundamental shifts in the
  MPU roadmap?
• A consistent and holistic modeling approach for
  MPU roadmap to reflect recent technology changes
  and to tradeoff MPU design constraints
• Historical MPU design constraints
• Moores Law TrN 2 ? (TrN-1)
• Constant die area 310mm2 ((2X Tr) ?
  (0.5X Tr area) 1)
• Power 130W 150W
• Performance improved with multicore
  architecture

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Technology Scaling Changes for ITRS 2009

• New scaling trends for M1 half pitch and gate
  length
• Cell area follows M1 half pitch
• Electrical parameter follows gate length
• Smaller area is expected, but what about power?

2 year delayed, but scaling becomes more
aggressive 0.7x / 3year ? 0.7x / 2year (2013),
0.7x / 3year (2014)
M1 ½ Pitch

• Decreases dimension
• Smaller area
• Decreases Pdyn and Pleak
• Increases density
• Increases Pdyn and Pleak

Physical Lgate
1 year delayed

• Electrical Parameters (Ioff, Cunit, etc.)
• Increases gate capacitance
• Decreases Ioff
• Increases Pdyn but decreases Pleak

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Parameterized MPU Model
M1 Half-Pitch (F)
A-Factor (Alogic , ASRAM)
Unit-Cell Area (Ulogic , USRAM)
Transistor Density (Dlogic , DSRAM)
Capacitance Density (Dcap,logic , Dcap,SRAM ,
Dcap,int)
Power Density (Ddynamic , Dstatic)
MPU Power (P)
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Updated A-Factors M1 HP (F) based Model

• Logic
• A-factor 175
• NAND2 Area
• 3 PPoly ? 8 PM2
• (3 ?1.5 PM1) ? (8 ? 1.25 PM1)
• 45 (PM1)2
• 180 F2 ? 175 F2

• SRAM
• A-factor 60
• SRAM Bitcell Area
• 2 PPoly ? 5 PM1
• 3 PM1 ? 5 PM1 15 (PM1)2
• 15 (2 F)2 60 F2

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Transistor Density Model

• (U) Area of unit cells
• Logic
• SRAM
• (S) Area of MPU
• Logic
• SRAM
• (D) Density of MPU (Tr. / Area)
• Logic
• SRAM

M1 Half-Pitch (F)
A-Factor (Alogic , ASRAM)
Unit-Cell Area (Ulogic , USRAM)
Transistor Density (Dlogic , DSRAM)
Capacitance Density (Dcap,logic , Dcap,SRAM ,
Dcap,int)
Power Density (Ddynamic , Dstatic)
MPU Power (P)
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Power Density Model

• Capacitance density
• Dynamic power density
• Active capacitancedensity
• Dynamic power density
• Static power density

M1 Half-Pitch (F)
A-Factor (Alogic , ASRAM)
Cg gate cap. per unit width from PIDS Cint
unit length interconnect capacitance from
INT Wg average width of a transistor
(5F) Dl,max maximum interconnect density (/cm2)
from INT, assuming every third
track is occupied
Unit-Cell Area (Ulogic , USRAM)
Transistor Density (Dlogic , DSRAM)
? switching ratio, assumed as 15 in 2007 ?
ratio of high performance (HP) transistors,
assumed as 10 ? ratio of SRAM dynamic power to
logic dynamic power
Capacitance Density (Dcap,logic , Dcap,SRAM ,
Dcap,int)
Capacitance Density (Dcap,logic , Dcap,SRAM ,
Dcap,int)
? of logic part uses HP transistors Bitcell
array (1/OSRAM) uses LSTP transistors ? of
peripheral part uses HP transistors (1- ?) of
peripheral part uses LSTP transistors
Power Density (Ddynamic , Dstatic)
Power Density (Ddynamic , Dstatic)
MPU Power (P)
PIDS Process Integration, Devices and
Structure INT Interconnect
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New MPU Integration Scaling and Chip Size

• Fast M1 half-pitch ? Increases density
• Number of cores 2x / 2year (2013), 2x / 3year
  (2014)
• Number of transistors per core 2x / 2year
  (2013), 2x / 3year (2014)

• Reduced A-factors
• Logic A-factor 320 ? 175
• SRAM A-factor 100 ? 60
• ? Reduced chip size
• 310mm2 ? 260mm2
• Logic area
• cores ? Logic Tr. ? AF2
• 100mm2
• SRAM area
• SRAM bits ? 9 ? 6 ? AF2
• 83mm2
• Integration overhead
• 30 of total chip size
• 77mm2

Billion Transistors
Intel Core-i7 263mm2 AMD Opteron (Shanghai)
258mm2
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Intrinsic Frequency Scaling

• MPU frequency scaling follows transistor
  intrinsic delay (CV/I) scaling
• 13 per year
• Dynamic power increases due to large active
  capacitance increases

• Dynamic power reduction techniques must be
  developed
• Switching activity ratio scaling factor ?N k
  ?N-1

k 1
k 0.95
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Power-Constrained Frequency Scaling

• Intrinsic frequency scaling activity scaling
• ? Still exceed 150W in 2015
• To meet market needs (130150W for a platform),
  frequency improvement has to be limited
• 13 per year ? 8 per year, total power lt 150W

Power lt 150W
8 frequency scaling
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Conclusion

• We have proposed a consistent, holistic modeling
  approach for MPU area/power/frequency
  roadmapping. From the model,
• For future high performance MPU, aggressive
  dynamic power reduction techniques are strongly
  required
• Frequency improvements need to be restricted 8
  per year
• Ongoing work
• We track tradeoff every year and make sure we
  dont miss the frequency/core/power curve
  tradeoff
• We are considering doing a 2009 blind survey on
  frequency from key vendors

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• BACKUP

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Outline

• International Technology Roadmap for
  Semiconductors
• Roadmap for Microprocessor
• Recent Technology Roadmap Changes
• Parameterized MPU Roadmap Models
• Transistor Density Model
• Capacitance Model
• Power Model
• Power-Constrained Frequency Model
• Conclusion

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History of ITRS
1991 Micro Tech 2000 Workshop Report
2009
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ITRS, System Driver, and MPU
Emerging Research Materials
Test Test Equipment
Modeling Simulation
Metrology
Design
Process Integration, Devices Structure
Process Integration, Devices Structure
Emerging Research Devices
Environment, Safety Health
System Drivers
System Drivers
ITRS

• Microprocessor (MPU) requires
• Leading edge process and device
• Highest frequency / integration / power
• We develop a power-constrained MPU roadmap to
  tradeoff power and performance

Interconnect
Interconnect
Yield Enhancement
Front End Processes
Assembly Packaging
Lithography
Factory Integration
RF and AMS
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Capacitance Density Model

• Capacitance density due to transistors
• Capacitance of a transistor
• Cg gate cap. per unit width from PIDS
• Wg average width of a transistor (5F)
• Capacitance density of transistors
• Capacitance density due to interconnect
• Dl,max maximum interconnect density (/cm2) from
  INT,
• assuming every third track is occupied
• Dl,eff effective interconnect density,1/3
  (Dl,max),
• considering routing congestion and
  power/ground network
• Cint unit length interconnect capacitance from
  INT

M1 Half-Pitch (F)
A-Factor (Alogic , ASRAM)
Unit-Cell Area (Ulogic , USRAM)
Transistor Density (Dlogic , DSRAM)
Capacitance Density (Dcap,logic , Dcap,SRAM ,
Dcap,int)
Power Density (Ddynamic , Dstatic)
MPU Power (P)
PIDS Process Integration, Devices and
Structure INT Interconnect
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Power Model Dynamic Power Density

• Active capacitance density
• Not all capacitances are working
• ? switching ratio, assumed as 15 in 2007
• Dynamic power density for logic area
• ? ratio of high performance (HP) transistors,
  assumed as 10
• Non-timing critical parts can have smaller
  activity (1/3?)
• Dynamic power density for SRAM area
• SRAM can have different (maybe slower) frequency,
  different operation modes, e.g., disabled,
  different VDD, etc. ? SRAM dynamic power
  estimation is hard!
• ? ratio of SRAM dynamic power to logic dynamic
  power

M1 Half-Pitch (F)
A-Factor (Alogic , ASRAM)
Unit-Cell Area (Ulogic , USRAM)
Transistor Density (Dlogic , DSRAM)
Capacitance Density (Dcap,logic , Dcap,SRAM ,
Dcap,int)
Power Density (Ddynamic , Dstatic)
MPU Power (P)
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Power Model Static Power Density

• Static power density for logic area
• ? ratio of high performance (HP) transistors,
  assumed as 10
• (1- ?) ratio of low standby power (LSTP)
  transistors
• Ioff,HP and Ioff,LSTP are from PIDS
• Static power density for SRAM area
• Bitcell array (1/OSRAM) uses LSTP transistors
• ? of peripheral part uses HP transistors
• (1- ?) of peripheral part uses LSTP transistors

M1 Half-Pitch (F)
A-Factor (Alogic , ASRAM)
Unit-Cell Area (Ulogic , USRAM)
Transistor Density (Dlogic , DSRAM)
Capacitance Density (Dcap,logic , Dcap,SRAM ,
Dcap,int)
Power Density (Ddynamic , Dstatic)
MPU Power (P)