The SPIRIT Consortium Specification Example Walkthrough

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The SPIRIT Consortium SpecificationExample
Walk-through
SlideSet Credit Christophe Amerijckx, ST
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Presentation Structure

• Introduction
• Component Description Leon UART
• Bus Component AHB Channel, AHB/APB bridge
• Bus Definition AMBA AHB
• Design Description A platform using Leon2 IPs
• Hierarchy
• Packaging IP with IP-XACT

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Introduction

• Presentation is based on a simple Leon platform

• To describe such a platform, we should be able to

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Presentation Structure

• Introduction
• Component Description Leon UART
• VLNV, Bus Interfaces, Memory Map, Model,
  Generators, Configuration Choices, File Sets
• Bus Component AHB Channel, AHB/APB bridge
• Bus Definition AMBA AHB
• Design Description A platform using Leon2 IPs
• Hierarchy
• Packaging IP with IP-XACT

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Component Description

• Leon2 UART XML describes
• Bus interfaces to the APB bus
• Memory mapped registers
• Views
• Signals
• Generators
• Configuration choices
• Files common Leon files and UART files

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Leon2 UART VLNV

• VLNV uniquely identifies a component by
  specifying

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Leon2 UART Bus Interfaces

• Bus Interface specifies

• Slave/master/system or mirrored

i_UART
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Leon2 UART Memory Map

• Memory Mapped Registers

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Leon2 UART Memory Map

• Memory Mapped Registers

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Leon2 UART Memory Map

• Memory Mapped Registers

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Leon2 UART Memory Map

• Memory Mapped Registers

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Leon2 UART Model

• Model section specifies
• View (vhdlsource)
• Signals
• Hardware parameters

for i_UART leon2_UART use entity
leon2_UART.leon2_UART(struct)end for
i_UART leon2_UART generic map (EXTBAUD gt
true)
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Leon2 UART Generators

• UART Generator specifies
• Name
• Parameter
• Access type
• Path to the generator executable

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Leon2 UART Configuration Choices

• Specify an enumerated list of elements to
  configure a parameter
• EXTBAUDChoice
• Choice in the UART
• False
• True

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Leon2 UART File Sets

• UART VHDL files compilation order
• ../../common/target.vhd
• ../../common/device.vhd
• hdlsrc/UART.vhd
• hdlsrc/leon2_UART.vhd
• Files could be binary
• Compiled library

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Presentation Structure

• Introduction
• Component Description Leon UART
• Bus Component AHB Channel, AHB/APB bridge
• Address Spaces, Bridge, Channel
• Bus Definition AMBA AHB
• Design Description A platform using Leon2 IPs
• Hierarchy
• Packaging IP with IP-XACT

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Channel Introduction (1/2)

• Connection between master and slave interfaces
  can be done
• With bus components containing channels
• Mirrored interfaces are associated with channels,
  making point to point connection to their
  non-mirrored partners
• Bus interfaces connected to a channel share a
  common address space
• Logic, decoding, remapping are possible within a
  channel

Bus


Slave

Master
S
M
MS
MM

• With direct connections
• For symmetric busses a master interface can
  directly be connected to a slave interface under
  some conditions

Master
Slave
M
S
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Channel Introduction (2/2)

• Connections between channels must be done with
  bridges
• address space associated with a master interface
  appears in a slave interface's memory map

Bridge
M
S
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Component AHB channel

• Main differences

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Component AHB/APB Bridge

• Main differences

Memory Map
Address Space
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Presentation Structure

• Introduction
• Component Description Leon UART
• Bus Component AHB Channel, AHB/APB bridge
• Bus Definition AMBA AHB
• Design Description A platform using Leon2 IPs
• Hierarchy
• Packaging IP with IP-XACT

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Design

• VLNV
• Component Instances
• Cores, busses, peripherals
• Interconnections
• between components

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Presentation Structure

• Introduction
• Component Description Leon UART
• Bus Component AHB Channel, AHB/APB bridge
• Bus Definition AMBA AHB
• Design Description A platform using Leon2 IPs
• Hierarchy
• Packaging IP with IP-XACT

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Hierarchy
MS
MS0
MS1
S
M
MM
MS2
S
MS3
APBSubsystem

• Changing the design to include an APB subsystem
  implies
• Making a design of the subsystem
• Make a component referencing that design (VLNV)
• Instantiate that component in the top level

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Hierarchy create subsystem design
MS
MS0
MS1
MM
S
M
MS2
S
MS3

• Making a design of the subsystem
• As a normal design, interconnect the different
  components and export the slave and mirrored
  slave ports
• Vendor spiritconsortium.orgLibrary
  Leon2Name APBSubsystemVersion V1.0

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Hierarchy create hierarchical component

• Making the hierarchical component
• View with reference to the design VLNV
• Put all exported signals
• Put all exported interfaces

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Hierarchy top level design
MS
S
APBSubsystem

• Instantiate the hierarchical component in the top
  level design this is done as any other component

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Presentation Structure

• Introduction
• Component Description Leon UART
• Bus Component AHB Channel, AHB/APB bridge
• Bus Definition AMBA AHB
• Design Description A platform using Leon2 IPs
• Hierarchy
• Packaging IP with IP-XACT

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Packaging IP with IP-XACT

• Packaging complexity depends on IP complexity
• Fixed IP
• easy to package and exchange since there are no
  configurable parameterse.g. an APB GPIO block
  with fixed base address
• Parameterised IP
• needs to define parameters support by EDA tools
  to customise the IPe.g. AHB/APB bridge with
  configurable bus-widths
• Configurable IP
• IPs created or modified by running an IP specific
  generatore.g. AHB bus fabric with selectable
  number of masters and slaves, and automatic
  generation of decoder

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Packaging IP with IP-XACT

• Design Tools will create IP-XACT packaging of IP
  since HW designers wont want to write XML (XML
  is not easy to read/write)
• Tools can help the user to package its IP in
  IP-XACT XML format by proposing a template the
  user can fill using one of the following
  techniques
• Automatically
• Signals can be retrieved from entity
• Some Hw parameters can retrieved from generics
• Sometimes, memory map can be retrieved from a .h
• Semi-automatically
• Bus Interfaces can be retrieved if, for example,
  each signal belonging to the same interface has
  the same pre/postfix and if we provide a mapping
  table (pre/postfix-interface)
• Manually

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Summary

• The examples showed
• Packaging of a component with a slave interface
• Packaging of a bridge with slave/master interface
• Packaging of a simple channel
• Packaging of a bus definition
• Description of a design
• IP-XACT contains much more
• CPUs, generators, SW (drivers, boot code)
  packaging, memory remapping, ...

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Thank You!
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