Min Pan, Cadence Design Systems, Inc'

1
IPR An Integrated Placement and Routing Algorithm

• Min Pan, Cadence Design Systems, Inc.
• Chris Chu, Iowa State University

Work partially supported by SRC under task ID
1206 and NSF under grant CCF-0540998
2
Motivation (1)

• Traditional Placement and Routing Flow
• Sequential Flow
• Need iterations due to routability or timing
  problem
• Inconsistency between placement and routing
• Inaccurate interconnect model used in placement
• Clique-Model, Star-Model, Bounding Rectangle
• Real routing implementation
• Steiner-tree, maze routing

3
Motivation (2)

• Congestion Estimation are widely used in
  congestion-driven placement but not accurate
  FastRoute - ICCAD06
• Different routing algorithm can result in very
  different routing congestion
• No general congestion estimator could obtain
  accurate routing congestion for all routers
• Accurate routing information cannot be obtained
  using any of the traditional interconnect models
  used in placement
• Inaccurate congestion
• Inaccurate timing
• Unable to consider buffering because of wrong
  interconnect topology

4
Motivation (3)

• It is necessary to integrate placement and
  routing together to achieve high-quality
  place-and-route solution and remove PR
  iterations
• Global routing is suitable for PR integration
• Globally allocate routing demand over
• resources, and generate interconnect
• info very close to the final routing
• implementation (WL, Topology, Cong.)
• Runtime is much faster than detailed routing
• Obstacle of PR integration
• High complexity, need manageable runtime
• Good trade-off between accuracy and runtime

5
FastPlace, FastDP and FastRoute

• FastPlace ISPD04, ASPDAC06, ASPDAC07
• A very fast quadratic placement algorithm based
  on
• Hybrid net model
• Cell shifting
• Iterative local refinement (ILR)
• FastDP ICCAD05
• A very fast detailed placement algorithm to
  optimize
• HPWL (Half Perimeter Wirelength)
• FastRoute ICCAD06, ASPDAC07
• An ultra fast Global Routing algorithm to achieve
  high-quality
• routing solutions
• Tens to hundreds times faster than traditional
  global routers

6
Integration Issues

• Maintain an accurate congestion view of placement
  during the placement procedure
• Cells are moving all the time during placement
• Routing need to be updated when placement changed
• Directly apply global routing during placement is
  notacceptable in runtime
• Adjust the routing accuracy according to
  different placement stages
• Cell positions are gradually refined from stage
  to stagein placement
• Routing accuracy should be adapted to the
  placement accuracy

7
IPR Flow Global Placement Legalization

• Global Placement
• 1. Repeat
• a. Solve convex quadratic program
• b. Perform cell-shifting and add spreading force
• 2. Until the placement is roughly even
• 3. Repeat
• a. Perform Steiner-WL based Iterative Local
  Refinement
• 4. Until the placement is even and no significant
  improvement on Steiner-WL
• 5. Run FastRoute to get an initial global routing
  and congestion map
• 6. Repeat
• a. Perform Routability Driven Refinement to
  reduce congestion
• b. Run incremental FastRoute to get updated
  routing and congestion map
• 7. Until no significant improvement on congestion
• Legalization
• 8. Move standard cells to legal positions and
  remove overlaps, minimize disturbance to the
  global placement

8
IPR Flow Legalization Detail Placement

• Detailed Placement
• 9. Run FastRoute to get initial global routing
  and congestion map
• 10. Repeat
• a. Apply Routability Driven Global Swap to reduce
  congestion
• b. Update routing and congestion map by rip-up
  and reroute trees
• 11. Until no significant improvement on
  congestion
• 12. Run FastRoute again to get global routing and
  congestion map
• 13. Repeat
• a. Apply Routability Driven Local Swap to reduce
  routing congestion
• b. Update routing and congestion map by rip-up
  and reroute tree branches
• 14. Until no significant improvement on
  congestion
• 15. Run final round of FastRoute to obtain the
  final PR solution

9
Global Placement Techniques (1)

• Quadratic Placement with Cell-shifting spreading
• Similar to FastPlace ISPD04, TCAD05, ASPDAC06
• To obtain good starting solutions for later
  stages
• Steiner-tree wirelength driven local refinement
• Steiner-tree wirelength has much better
  correlation to final routing wirelength than
  widely used HPWL
• Locally search good locations for cells to reduce
  Steiner-tree wirelength
• Employ FLUTE ICCAD04, ISPD05 to compute
  Steiner-tree wirelength efficiently

10
Global Placement Techniques (2)

• Routability Driven Refinement (RDR)
• Work on a relative stable placement
• Each move is relatively small
• Only update the tree branches connecting to the
  moving cell

11
Legalization (optional)

• Put all cells in legal positions
• Similar to FastPlace
• Minimize disturbance to maintain the good
  routability enabled by global placement

12
Detailed Placement (1)

• Routability-driven Global Swap (RGS)
• Try all the cells in the optimal region ICCAD05
• Only update the routing trees being affected

Optimal region
j
i
j
i
i
j
i
j
13
Detailed Placement (2)

• Routability-driven Local Swap (RLS)
• Swap with 4 neighboring cells
• Only route the tree branches being affected
• Faster than RGS

14
Experiments Setup

• Benchmark IBMv2 suite
• Only work on the hard cases
• Routing grid 660x560 as in original LEF/DEF
• To make the testcases harder, capacity for V and
  H areadjusted to 16 and 14, respectively, from
  original 20
• Linux workstation with 3.0GHz Intel Pentium 4
  CPUand 2GB memory
• Flows to compare
• 1. Integrated PR approach (IPR)
• 2. ROOSTER ISPD06 FastRoute2.0
• 3. Routability-driven FastPlace FastRoute2.0
• 4. FastPlace FastRoute2.0

15
Experimental Results
16
Experimental results (2)
17
Conclusion and Future Work

• Conclusion
• Integrated Placement and Routing approach can
  eliminate the inconsistency between the
  interconnect models used in placement and routing
  stage
• Integrated Placement and Routing approach is
  feasible and necessary to achieve high-quality
  Place-and-Route results
• Future Work
• Improve the quality and efficiency of the
  algorithm
• Apply the framework to timing, buffering and
  signal integrity problems

18
Thank You ! Questions?