Scan design techniques

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Scan design techniques

• J. M. Martins Ferreira
• FEUP / DEEC - Rua Dr. Roberto Frias
• 4200-537 Porto - PORTUGAL
• Tel. [phone] / Fax [phone]
• (jmf_at_fe.up.pt / http//www.fe.up.pt/jmf)

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Objectives

• To introduce the basic concepts in design for
  test
• To prepare the introduction of the standard
  boundary-scan test architecture

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Outline

• Testability and test generation in sequential
  circuits
• Testability improvement via ad hoc solutions
• Structured approaches to design for testability

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Test generation for sequential circuits

• Direct application of the D-algorithm leads to
  the combinational circuit inputs and outputs, not
  necessarily to primary inputs or outputs

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Test generation - step 1
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Test generation - step 2
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Test generation - step 3
The second clock cycle is applied with

A1 and guarantees fault detection,
because the circuit is now brought to a
state where fault activation and fault
propagation are simultaneously
possible.
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The general case is however much more complex...

• The D-algorithm does not necessarily lead to
  circuit primary inputs and outputs
• Knowledge of the state transition diagram is
  required
• It may happen that the fault affects the state
  transition diagram, in which case the required
  sequence at the circuit primary inputs becomes
  even harder to find

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The case of Y s_at_0

• Test vector generation for a fault that affects
  the state transition diagram will help us to
  understand the problem

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The case of Y s_at_0 (cont.)

• Modification in the state transition diagram

Q1
Q0
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Ad hoc testability improvements

• Design rules or amendments to avoid or minimise
  test vector generation problems
• Major drawbacks
• Not always reusable
• Testability depends largely on the type of circuit

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Some ad hoc testability rules

• Split counters to avoid high numbers of clock
  cycles until the required output combination is
  achieved
• Include reset and preset lines (synchronous or
  asynchronous)
• Partition large circuits and add extra inputs and
  outputs for direct controllability and
  observability of internal nodes

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Structured Design for Testability (DfT)

• Structured DfT methodologies enable a simple way
  to drive the circuit to any given state in a
  fixed (and short) number of clock cycles
• Does structured DfT have drawbacks?
• Design rules (design styles) have to accepted
• Additional silicon area, more pins and higher
  propagation delays but is this an additional
  cost?

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The scan design principle

• The scan design principle consists of inserting a
  21 multiplexer between the input of every D
  flip-flop and its driving logic

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Scan design advantages (1)

• Problem Part of the combinational circuit inputs
  are not directly controllable, since they come
  from the D-FF outputs (these nodes define the
  present state of the circuit)
• Solution Scan flip-flops enable direct
  controllability of the D-FF outputs through a
  simple procedure with a fixed number of clock
  cycles

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Better controllability through scan design (1)
Example Take the circuit to state 110, starting
from state 100 (intrusive)
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Better controllability through scan design (2)
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Better controllability through scan design (3)
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Better controllability through scan design (4)
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Better controllability through scan design (5)
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Scan design advantages (2)

• Problem Part of the combinational circuit
  outputs are not directly observable, since they
  go to the D-FF inputs (these nodes define the
  circuit next state)
• Solution Scan flip-flops enable direct
  observability of the D-FF inputs through a simple
  procedure with a fixed number of clock cycles

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Better observability through scan design (1)
Example Observe the next state (eventually
non-intrusive)
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Better observability through scan design (2)
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Better observability through scan design (3)
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Better observability through scan design (4)
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Better observability through scan design (5)
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DfT Eventually an overhead

• The 21 muxs increase the propagation delay and
  require additional silicon area and pins, but
  will this increase cost?
• How do we quantify the benefits of easier test
  vector generation and application?
• Design freedom was traded for higher testability,
  but partial scan design might be a preferred
  intermediate solution