OptimalComplexity Optical Router

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Optimal-Complexity Optical Router

• Hadas Kogan, Isaac Keslassy
• Technion (Israel)

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Router schematic representation
Router
Optic to electronic
Electronic to optic


Optic to electronic
Electronic to optic

• Problem - electronic routers do not scale to
  optical speeds
• Access to electronic memory is slow and power
  consuming.
• Data conversions are power consuming as well.

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Power consumption per chassis
Nick McKeown, Stanford
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How about an optical router?

• No electronic memory bottleneck
• No O/E/O conversions
• BUT
• An optical router is thought to be too complex.
• Is it?

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• Objective quantify the fundamental complexity of
  an optical router

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Quantifying complexity

• Quantify the fundamental complexity of an
  optical router ? reduce into most basic
  building blocks
• Switching 2x2 switches(and input/output lines)

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Basic optical buffering component

• Buffering 2x2 switches (and input/output/fiber
  delay lines)
• Mode of operation
• (a) Write
• (b) Circulate
• (c) Read

(a)
(b)
(c)
1
1
1
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• The complexity of a system is the minimal number
  of 2x2 switches needed to implement it.

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Quantifying complexity

• Complexity lower-bound To get a state-space of
  size K in time T, the minimal number C of 2x2
  switches needed is
• Examples
• NxN switch
• Time Slot Interchange with time frame N

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Quantifying complexity

• A construction algorithm is said to be optimal if
  its number of 2x2 switches grows like the
  construction complexity.
• Examples
• NxN switch (Benes is optimal)
• Time Slot Interchange

Benes 65
Jordan et al. 94.
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Optimal buffer emulation

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Emulation definition

• Original buffer
• Buffer emulation (with delay D)

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5
4
3
2
1
t
D
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Emulation idea

• Objectif emulate buffer of size B
• Universal buffer any policy
• Idea schedule using frames of size B
• During any frame of B slots, observe which
  packets leave the original buffer and color them
  in blue
• After some pipeline delay, send these blue
  packets in the same order

F - Frame of size B
Frame-based scheduling
Optical buffer
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Algorithm
departure
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B
5
2

• Algorithm is optimal
• Complexity T(ln B)
• Complexity lower-bound T(ln B) (the Time Slot
  Interchange is a special case)

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Optimal router emulation

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What we want an ideal router

• An output-queued push-in-first-out (OQ-PIFO)
  switch.
• OQ - Arriving packets are placed immediately in
  the queue of size B at their destination output.
• PIFO packets departure ordering is according to
  their priority.

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What we want an ideal router

• Why it is ideal
• OQ Work-conserving ? best throughput and average
  delay.
• PIFO Enables FIFO, strict priority, WFQ
• But up to N packets could be destined to the
  same output
• Speed-up for switch
• Speed-up for queue
• PIFO is hard to implement.

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Finding the complexity

• Direct calculation of complexity seems impossible
  what are the states?
• Alternative way of finding the complexity
• Find a lower bound
• Find an upper bound via algorithm
• Algorithm complexity T (lower bound) ?
  algorithm is optimal

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Lower bound - intuition
B
At least T(Nln(N))
At least T(ln(B))

• Intuition the complexity of an OQ-PIFO switch is
  at least T(N ln(N) N ln(B)) T(N ln(NB))

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Lower bound

• A frames switch (time/space switch)

t1
t2
t3
t4
t5
t6
t3
t4
t5
t6
t7
t8
t9
Frames switch
1
2
3
7
8
9
N
6
2
5
11
9
10
4
5
6
10
11
12
3
4
1
12
7
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B

• A frames switch is a special case of an OQ-PIFO
  switch.
• The practical complexity of a frames switch?
  Complexity OQ-PIFO T(Nln(NB))
• Now, find an algorithm that reaches this
  lower-bound

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Solving the speed-up problem
Leaves output A at time 1

• Example Emulating a non-idling OQ-FIFO switch

D1
Output A
Input 1
A1

Output B
C1

A2
Input N
C2

• Using parallel buffers to resolve conflicts
• At most one packet can enter a buffer at each
  time slot (N-1 constraints).
• A packet departing at time T should not enter a
  buffer with a packet departing at T (N-1
  constraints).
• ? 2N-1 buffers are enough.

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The pigeonhole principle

• Proof intuition
• Pigeons ? Packets
• Holes ? Buffers
• For emulating PIFO behavior
• The departure process is slightly modified
• 4N-2 parallel buffers are required

Input 1
Output 1



Input N
Output N
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An optical emulation of an OQ-PIFO switch
The pigeonhole principle Our emulation of an
optical buffer An optical OQ-PIFO switch
Optical buffer
Output 1


Output N
Optical buffer
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An optical emulation of an OQ-PIFO switch
(4N-2)xN switch
Nx(4N-2) switch
B
pB
pB
B
B
pB
pB
B
...
B
pB
pB
B

• Number of 2x2 switches T(NlnNNlnB)
  T(Nln(NB)) T(lower bound)? algorithm is
  optimal

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Conclusion

• Buffer fundamental complexity T(lnB)
• OQ-PIFO router fundamental complexity T(NlnNB)
• Both can be reached using given algorithms

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Thank you!