Virtual Platforms The way forward for great partnerships and integrated ecosystem offerings

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Virtual PlatformsThe way forward for great
partnerships and integrated ecosystem offerings

• Kaveh Massoudian, IBM, 5/22/2008

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Background

• Simulation Technology advancements are benefiting
  all phases of system development and are now an
  inherent part of a best of breed product design
  methodology
• Recent growth in complexity of Embedded System
  Designs (HWSW) requires a fundamental new
  approach and Simulation provides a promising
  path.
• ASSP and SoC designs require a more efficient way
  of integrating IP blocks from different providers
  and then get the correct SW stack and components
  to deliver optimal solutions to customer in the
  fastest time possible.
• Collaborative approach is the best way to achieve
  all these objectives and allow for breakthrough
  innovations along the way.

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Vision

• Simulation Technology as enabler of better
  designs and expansion of business
• Simulation as a verification vehicle.
• Simulation as a preferred software development
  platform.
• Simulation as a means for software-hardware
  co-design.
• Simulation as a means to explore new SW paradigms
  (like multi-core, accelerator offload, etc.) in
  early concept and architecture phases that can
  then be used to optimize the HW design.
• Simulation as an Architecture Workbench to allow
  for system design option space analysis
  (performance, power/thermal efficiency, function
  splits, etc.).
• Simulation Models as an upfront vehicle for
  specification of the design which will then be
  used by both HW and SW teams.
• Simulation methodology as motivation to deliver
  virtual components for rapid system prototyping
  at lower expense than real hardware.
• Simulation as a means to deliver virtual
  platforms when real HW is either not available or
  is too cost prohibitive or for examining
  alternative configurations.

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Simulation Spectrum
Level of Model Abstraction
SW Verification against HW spec
Behavioral
Main Chip Verification Environments
RTL
Low Level Design Analysis
Speed of Simulation
Netlist
HW based emulation (FPGA, etc.)
Event or Cycle Sim (SW based)
SystemC
Spice
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High Level ESL Flow for Embedded Systems
Initial Application Specification
V E R I F I C A T I O N
System Level Co-Design And Tradeoff Analysis
(High Level) Software Specification
High Level Hardware Architecture
System Level Hardware Design
System Level Software Design
Detailed Hardware Design (Function
Communication Architecture)
Embedded Software Image
Hardware/Software Integration
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The right level of abstraction
1,000
TLM
System Developer
100.0
Performance in mega MIPS
10.0
Hardware Developer
Software Developer
VHDL
0.100
From cycle accurate to functional accurate
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Componentized Software Architecture Example
Solution Oriented Middleware/Applications
Maint. Partition
Client (Local) Functions
Server Functions
Portal
Device Management (SW Update, Config.)
Autonomic Function (Self-Config. / Self-healing)
Home Security
TV Phone
VoIP Appl.
Media Editor
Data Mining
EPG
Recorder
Player
Config Utility
Browser
Java Applications
Music
Video
org.eclipse.swt.browser
Picture
Streaming Server
APIs
OCAP/ACAP
BD-J
Web Container
Web Services
MHP
Channel / Tuner (Zapping)
Content Protection
Java 3D
ARIB / ATSC / DVB
Content Mgmt
Transcoding
SIP / H.323
CODECs
Crypto Engine
GTK / Qt/E
eSWT
GEM
Embedded Database
OpenGL ES
DirectFB
OSGi Service Platform
JVM
Voice Reco./Synthesis
Graphic Library
Biometrics
HTTP(s)
UPnP AV
RTP
RTSP
Network Protocols
UPnP
RTCP
HTTP(s)
TCP UDP
IPv4/IPv6
IPv4/IPv6
Power Mgmt
SE Linux
ACC Mgmt
Security
Linux 2.6. x CE Linux
Tiny OS
Ethernet
Tuner
Wireless
Blu-ray
USB
1394
HDMI
DVI
Hypervisor
POWER ARCHITECTURE cores
VMX Accelerator
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• Architecture Workbench
• Allow exploration of SoC designs to find the
  optimal solution.
• Document IP blocks and systems design in machine
  readable format
• Seamless integration of tools
• Automate flows and generate verification
  environments
• Abundance of reusable IP
• Componentized HW IP

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Virtual Platform - the center of the Ecosystem
Runs in Simulation Environment
Rapid Prototyping and Proof Points
Software Assets
Componentized S/W Architecture
Linux Applications
Java Applications
Maintenance
Decode
Encode
Networking
Middleware
JVM
High-End Digital TV
Math Lib
Security
Networking / DLNA
Linux / RTOS / Device Drivers
Firmware / Hypervisor
Set top Box
New hardware support
Automotive
Software Models of Cores
405
440
Desktop AV Box
NG
Modeling
On Flexible HW Configuration
Virtualized Hardware Pool Componentized HW
Architecture
SPE
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Benefit to SoC eco - Virtual Platforms On-Demand
Traditional approach
Virtual Platforms
(e.g. AMCC)
Build a virtual board on-demand
405EP Board 405EX Board 405EXr Board 405EZ
Board 405GP Board 405GPR Board 440EP Board 440EPx
Board 440GR Board 440GRx Board 440GX Board 440SP
Board 440SPe Board 460EX Board 460GT Board

• Variety of physical evaluation boards
• Huge investment on hardware
• Still uncovered combinations

• Any virtual boards on-demand
• The only economical way to cover wide-range of
  products

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Virtual Platform Benefit Faster Time to Market
Legacy Development
Need to wait for HW availability
Additional SW Dev.
Base SW Enablement
ePlatform based Development
Faster Time-to-Market

• Parallel development of hardware and software
  drastically shorten a total development period.

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Power.org for creating and nurturing the
ecosystem

• Core/ASSP
• AMCC, Freescale, IBM,
• EDA Tool and IP providers
• Cadence Design Systems, Synopsys, Denali
  Software,
• Simulation and Modeling
• VaST Systems, Virtutech, Synopsys, CoWare
• OS / Software Dev Tools
• MontaVista, Wind River, GreenHills, CodeSourcery,
  Lauterbach Datentechnik, LinuxWorks, Terra Soft
  Solutions
• Applications and Middleware
• IBM, HCL America, Mercury Computer, others
• Industry Solutions
• Ericsson (Telecom), Sony (Consumer Electronics),
  Thales (Aerospace and Defense), XGI (Multimedia)

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Virtual Platforms and Simulation TSC deliverables

• Relevant Standards integration
• OSCI and TLM 2.0, SPIRIT and IP-XACT , Accellera
  and SCE-MI 2.0
• Extension to standards and guidelines as needed
• First attempt will always be to work through
  existing or relevant standards bodies.
• Interfaces and Calling Conventions for processor
  and device modeling
• Define the support of models at different levels
  of abstraction
• Mixed-abstraction level simulation platforms thus
  supporting legacy IP
• Consolidated modeling and tools portal as part of
  the solutions portal
• One stop shop to provide access to the different
  models available at various levels of abstraction
  that support the POWER architecture
• Virtual Reference Platform solution that
  leverages and integrates the Power.org technical
  and marketing initiatives
• ePAPR, CDI, embedded Hypervisor, Embedded SW
  framework, solutions portal

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Invitation to all partners to join

• All input is welcome and will be most valuable
• Please join us in this collaborative innovation
  effort

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Some observations and discussion points

• While event or cycle simulation can also be done
  using a post-synthesis netlist, it is normally
  performed at the RTL level, and instead other
  tools are used to verify that the post-synthesis
  netlist does indeed match the RTL model.
• There is good amount work going on in doing logic
  synthesis from behavioral style SystemC models,
  and while some claim success, it appears that
  this not ready for pervasive usage yet.
• For these synthesis tools to work effectively the
  SystemC must be written in a sort of RTL style of
  programming.
• However, that does not seem like a wise use of
  the SystemC language because of the loss of
  abstraction.
• Also, the VHDL, Verilog and SystemVerilog
  languages already provide excellent means for
  writing at the RTL level.
• Over time, SystemC-to-synthesis might become more
  popular, depending upon the advancement of the
  EDA tool capabilities and the acceptance of the
  logic/system design community for coding in C.
• SystemVerilog is a competing option which may
  prove to be the winner for these designers.

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Device Modeling Standardization Layers
High Level Language
Work in progress
API / Interface
Configure
Shared Object Code
Implement Config