Loop Filter Optimization

1
Loop Filter Optimization

• Dean Banerjee
• Deborah Brown
• Khang Nguyen

2
Overview

• Introduction
• PLL Loop Filter Design Issues
• Common Method for Loop Filter Design and
  Optimization
• New Approach for Loop Filter Design and
  Optimization

3
Loop Filter Design Issues

• Spur Level vs. Lock Time Tradeoff
• Loop bandwidth
• Phase margin
• Pole ratios
• Filter Order

4
Loop Bandwidth

• Smaller Larger
• Loop Bandwidth Loop Bandwidth
• Lower Spurious Noise Faster Lock Time

5
Phase Margin

• Relates to stability of system
• Typically ranges from 40 to 55 degrees
• Higher phase margin results in more stable
  system, but if too high can cause increased lock
  time
• For minimum RMS phase error designs, 50 degrees
  is a good starting point

6
Pole Ratios

• T3/T1 ratio and T4/T3 ratio
• Higher pole ratios
• Less spurious noise
• Decreases value of highest order capacitor
• Watch out for VCO input capacitance

7
Filter Order

• Benefits of higher filter order
• Lower spur levels
• Drawbacks of higher filter order
• More passive components
• More resistor noise due to added resistors
• VCO capacitance more likely to cause distortion

8
PLL VCO Selection

• PLL Selection
• Covers the frequency range
• Divide Ratios supported by N and R counters
• Why would I choose one part over another?
• VCO Selection
• VCO Gain
• VCO input capacitance
• Adds in parallel with highest order loop filter
  capacitor.
• Can cause problems if highest order loop filter
  capacitor is too small.
• Phase Noise vs. Tuning Range Tradeoff

9
Common Method for Loop Filter Design and
Optimization

• Choose arbitrary values for filter parameters,
  calculate filter components, and then analyze.
  If loop filter does not meet lock time and spur
  requirements, then adjust filter parameter values
  and re-optimize.

10
Disadvantages of Common Method

• Iterative Process
• Very time consuming
• Very tedious
• Based on trial and error
• Does not always achieve the optimal solution

11
New Approach for Loop Filter Design and
Optimization

• Give me the best loop filter that meets my lock
  time and spur level requirements.

12
Four Easy Steps Using theNew Method

• Define System Level Parameters
• Determine Loop Filter Design Parameters from
  System level parameters
• Determine Loop Filter Components from Loop Filter
  Design Parameters
• System Level Performance from Loop Filter
  Components

13
Introduction to EasyPLL

• Allows you to
• Specify your PLL system requirements
• Choose the best parts that meet your
  requirements.
• Determine your Loop Filter Components
• Analyze the simulation results
• Examine various wave forms
• Change parameters in any order
• Order a Custom Eval Board when you are done.

14
Get Loop Filter Parameters

• The old way was to just pick a phase margin and
  loop bandwidth by rules of thumb and experience
• EasyPLL picks all parameters in an optimal way to
  ensure that the system parameters are met
• EasyPLL picks which phase margin yields the
  fastest possible lock time

15
Design Loop Filter

• EasyPLL chooses time constants in an optimal way
  that typically can result in up to a 30
  improvement in lock time
• EasyPLL exactly solves for all component values
  (except 4th order filters, for which it
  approximates)
• EasyPLL returns exactly what is specified

16
Determine System Level Performance

• EasyPLL also simulates all results so that the
  design can be double checked
• The impact of rounding component values to
  standard values can be seen
• EasyPLL provides detailed and complete simulations

17
Four Easy Steps in EasyPLL
18
Choose a PartEnter System Requirements
1 2
3
19
Choose a PartSelect a PLL and VCO
1
2
3
20
Create a DesignEnter Performance Requirements
-Phase Margin -Loop Bandwidth are set to AUTO
3
-Optimize for Lock Time and set constraints
1 2
2nd Order Filter
21
View Component Values
-Phase Margin chosen as 49.2 deg -Loop
Bandwidth chosen as 8.7 KHz
- Lock time achieved - Spur gain missed
22
Increase to 3rd Order Filter
-Phase Margin adjusted to 45.5 deg -Loop
Bandwidth adjusted to 8.6 KHz
- Lock time achieved - Spur gain achieved
Change to 3rd Order Filter
23
Analyze a Design Locktime

• Viewing the Lock time graph verifies that we met
  our Lock time requirement of lt300uS

24
Analyze a Design Spur Level

• Running the Spur Estimate simulation verifies our
  Spur Gain of -5 dB at a 500 KHz offset and a
  corresponding Spur Level of -86 dBc.

25
Analyze a Design Bode Plot

• The Bode Plot graph shows the Phase Margin and
  Loop Bandwidth that were calculated for you by
  EasyPLL.

26
Build It Design Check

• Run the Design Check to make sure its a good
  design
• Valuable tips on how to improve your design.

27
Build It Order Custom Board

• Review the Bill of Materials
• Click on Order Custom Board
• Enter your credit card information
• Custom/tested board will be shipped within 5
  business days.

28
Final Result
29
Conclusion

• New Approach for Loop Filter Design and
  Optimization
• Quicker design time
• Optimized loop filter designs
• No more guessing!
• Design your loop filter in minutes rather than
  days

30
Where to Find More Information

• WIRELESS.NATIONAL.COM home page
• Links to techonline server archive of this
  presentation
• Deans book PLL Performance, Simulation and
  Design Handbook, 2nd Edition!