A DFM Aware Spacedbased Router

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A DFM Aware Spaced-based Router

• David Cross, Architect
• Eric Nequist, Fellow
• Louis Scheffer, Fellow
• ISPD07
• March 21, 2007

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Agenda

• Introduction
• Nanometer Challenges
• An Incremental, Electrically and Manufacturing
  Driven Architecture
• Cadence Space-based Router
• Summary

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What is the Space-based Router?

• Clean-sheet-of-paper router and layout
  infrastructure
• Along the lines of IC Craftsman (CCT) Virtuoso
  Chip Assembly Router
• But uses much less memory and is significantly
  faster with higher capacity
• Design closure as a top-level objective
• Incorporates manufacturing and methodology
  know-how
• Developed in collaboration with IBM
• New Infrastructure
• Callable DFM, extraction, and timing models
• Supports multi-processing
• OpenAccess, graphics processor support
• New Algorithms
• DFM rules, adaptive refinement multi-processing
• New Data structures
• Gridless, all operations incremental, handles
  45s, multi-processing

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Nanometer Challenges
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Evolution of design rules by process node

• gt130 nm.
• Simple different-net spacing rules, usually with
  only one wire width routed (except maybe power).
• Same-net rules limited to min spacing.
• Because the routing pitch is usually via-via or
  line-via, grid-based abstractions work well.
• 130 nm.
• More complex different-net spacing rules.
  Multiple wire widths and via sizes make
  grid-based abstractions complex.
• Fairly simple same-net rules.

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Evolution of design rules by process node

• 65-90nm.
• Complex different-net rules, including
  width-length spacing rules. Often more than four
  or five routed wire widths.
• Double cut vias for yield enhancement.
  End-of-line rules require larger spacing between
  parallel small edges. Proximity based cut-to-cut
  rules, parallel cut-to-cut rules.
• Difference between best and worst case spacing
  from 10-15x.
• Complex same-net rules with 2 and 3 edge min-edge
  rules, min-num-cut rules.

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Evolution of design rules by process node

• lt45nm.
• Discrete different-net rules spacing and width
  rules.
• Extremely complex same-net rules end of line
  rules include very restrictive single edge
  min-edge rules which require larger spacing of
  any edge less than 2 routing pitches. This
  requires wrong-way routing to either have larger
  spacing, larger width, or both.
• Proximity to wide wires changes spacing rules and
  min-num-cut rules.

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End-of-line spacing

• At 65 nm, requires larger spacing, but does not
  affect routing density significantly.

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Width-based spacing rules

• At 65 and 45 nm, requires larger spacing if
  wider objects interact.

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Min-edge rules

• At 65 and 45 nm, requires larger spacing if a
  certain number of adjacent edges are too small.

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Proximity-based min-num-cut rules

• At 65 and 45 nm, requires larger vias when
  attaching to wider objects or near wider objects
  (void migration)

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Discrete min-spacing rule

• At 45 nm, min-spacing rules may have illegal
  ranges that are greater than the min-space itself
  (forbidden pitch)

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90nm/65/45/32nm silicon manufacturing issues
2007
2005
2006
45 nm
65 nm
90 nm
130nm
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Direct support of design closure

• Traditionally, routers have been point tools that
  take a flattened net-list, some priorities and
  complete the routing connections minimizing DRC
  errors. Then all the routing is passed all at
  once back to the analysis tools.
• There is little consideration of timing
  trade-offs (requiring integrated extraction for
  RC modeling), or manufacturing trade-offs
  (requires integrated CMP modeling and Litho
  modeling).
• At best, all the routing is put in a large (and
  slow) optimization feed-back loop to improve
  timing, noise, and manufacturing issues with
  little assurance of converging these trade-offs
  or providing feed back of convergence issues.

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An Incremental, Electrically and Manufacturing
Driven Architecture
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Integration of router with other functions

• Router shares a data model with DRC checking, RC
  extraction, CMP modeling, CAA modeling, and litho
  modeling.
• Single incremental data model (which supports
  multi-processing as well) that allows tight
  optimization of all design trade-offs with good
  control of convergence.
• Fully hierarchical model does not require
  abstracted layout, supports flat, hierarchical
  and device level layout.
• Additional different-net and same-net rules are
  easy to support because there is no assumption of
  mapping them to a abstract model.
• Advanced rule support allows use of optional
  yield enhancement rules to avoid manufacturing
  and litho violations directly
• Native sign-off quality design rule checking

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Supports closure directly

• Supports both batch constraint driven design,
  and incremental closure of individual
  connections.
• The speed of the system is tied to the extent of
  the layout change. Thousands of shapes can be
  changed and evaluated in minutes, millions in
  hours.
• Many components like design rule checking, RC
  extraction, and layout optimization support
  multi-processing for even faster turn around
  time.

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External model support

• Can tightly integrate 3rd party DFM models too.
• Working with Litho Modeling and simulation
  suppliers to support litho hot spot fixing. Can
  use hints from these tools or apply our own
  recipe/advanced rules for fixing litho errors.

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Manufacturing Models Tied to Implementation
Manufacturing Models are complex Hard to
build Hard to qualify Before, you could use
conservative rules in the router, and full rules
in signoff But with complex models, this implies
either huge guardbands, or finding errors at the
signoff check. Need to (optionally) use the same
model for routing and signoff for final
closure Faster, less accurate derived model may
be used as well
Global routing
Corridor routing
Detailed routing
Manufacturing Models
DFM optimization
DFM Aware Space Based Implementation
CMP
Mfg Check
Extraction (Var Aware)
Timing/SI (SSTA)
DRC/LVS
Pwr/Therm
Litho
Etch
Timing DFM-correct GDS
CAA
RET
Litho Verif
CMP Density Verif
Manufacturing / Operations
Fracturing
Silicon
Yield Ramp
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Space-based Routing
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Changes from previous routers

• Infrastructure
• Updates for performance (graphics processors)
• Updates for software engineering (OpenAccess,
  XML, etc.)
• Algorithms
• Adaptive refinement different nets (or portions
  of nets) may co-exist at different levels of
  refinement
• Critical net may be fully embedded
• Noise sensitive net might know neighbors, but not
  location
• Non-critical net might be unrouted or global
  routed
• Data Structures
• Space tiles represent all area on a layer used
  and unused
• Memory grows proportional to number of shapes,
  not grid intersections.
• Neighbor queries are always fast
• Updates proportional to area updated
• Good match for DSM manufacturing models

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Context-based, Adaptive Model Resolution

• In the Design
• Critical and sensitive paths need full
  resolution others do not

• In the Flow
• Adaptive model resolution to match abstraction
  level

RTL Synthesis
Model Resolution
Prototyping
Physical Synthesis
Global Routing
Corridor Routing
Nets/Paths
Detailed Routing
Optimization
Sign-off
Regions
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Context-based, Adaptive Model Resolution

• In the Flow
• Adaptive model resolution to match abstraction
  level

• Concerns of each step
• Global Routing Timing, Noise and CMP
  optimization
• Corridor routing Noise, CMP optimization, DRC
  correct
• Detailed Routing DRC correct, Litho, CMP, CAA
  optimization
• DFM Optimization DRC correct, Litho, CMP, CAA
  optimization
• Extraction, Timing Variation, CMP, Litho aware
• DFM/Y Scoring Weighted scores

RTL Synthesis
Model Resolution
Prototyping
Physical Synthesis
Global Routing
Corridor Routing
Detailed Routing
Optimization
Sign-off
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Route refinement

• Routing refinement by net and connection
• Allows continuous step-wise refinement of pieces
  of routing to different accuracies
• No switch-boxes or area boundary artifacts
• Allows context based model evaluation with
  timing, noise, and manufacturing models
• Routing of each connection can be composed of
  several steps, typically global routing,
  corridor routing, and detailed routing.
• Connections do not proceed in lock-step
• At any given time a connection could be composed
  of un-routed, global routed, corridor routed, and
  detail routed sections.

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Global Routing

• Assigns layers, relative topologies, and coarse
  location of the routing.
• This step may not be run on all connections,
  since some individual connections may be directly
  embedded by the detailed router.
• Layer assignment and hard/soft rules are used to
  provide the best global plan that meets the
  timing, noise, and CMP constraints.
• Very accurate congestion modeling, including pin
  access.

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Corridor Routing

• Assigns the exact relationship between wires
• A form of graph based routing.
• Uses global routes to restrict detailed routing
  locations.
• Can embed over 95 percent of the connections by
  length, in a runtime comparable to global
  routing.
• Difficult short connections are left for the
  detailed router.
• Allows direct consideration of noise constraints,
  timing constraints, and CMP effects since it can
  control the exact spacing between wires and which
  wires are adjacent.

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Detailed routing

• Supports short and long connections
• Short partial connections after corridor route
• Chip-level connection as large as thousands of
  routing pitches (for ECOs, for example)
• DRC/Manufacturing constraints are NOT abstracted
  to a grid, allowing creation of detailed wiring
  that meets these constraints without restricting
  the layout patterns.
• Supports an unlimited number of wire widths,
  spacing rules, vias and other constraints.
  Supports hard, soft, and taper rule
  specifications, by connection.
• Supports analog routing constraints, such as
  symmetric routing, shielding and stranding.

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Detailed routing

• Basic algorithm is A with assorted improvements
• The connection search in the detailed router
  searches the space tiles to find a set of optimal
  spaces that implement the connection subject to
  the routing constraints.
• These spaces are then used to embed the actual
  wires and vias subject to same-net rule
  requirements.
• Can snap layout to any manufacturing or imposed
  grid

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Space-based Routing

• Example of M1 to M1 connection

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Space-based Routing

• M1 space tiles

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Space-based Routing

• M2 space tiles

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Space-based Routing

• M3 space tiles

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Space-based Routing

• Completed search corridor

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Space-based Routing

• Route drawn in search corridor

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Summary of the Space-based Router

• New gridless router on a modern infrastructure
• Supports design closure as directly as possible
• Ties together routing, manufacturing models and
  electrical analysis on a common data model
• Incremental, supports multi-processing
• Generates robust, minimally guard-banded,
  high-yielding designs for 65nm and below.

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