Power Optimization in VLSI Design : Tunable Level Shifter

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Power Optimization in VLSI Design Tunable
Level Shifter
Abu Baker
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Outline

• Objective and Background
• CMOS Power Dissipation
• CMOS Device Characteristics
• CMOS Current Mirror
• Design of Level Shifter
• Circuit Simulation
• Delay and Power Analysis
• Leakage Analysis
• Comparison Analysis
• Summary and Discussion

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Outline

• Objective and Background
• CMOS Power Dissipation
• CMOS Device Characteristics
• CMOS Current Mirror
• Design of Level Shifter
• Circuit Simulation
• Delay and Power Analysis
• Leakage Analysis
• Comparison Analysis
• Summary

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NTRS Technology trends 200-300M chips by 2010
(0.07 micron CMOS)
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Energy/Power Gap
Dynamic Growth
Exponential growth in the of devices per chip
Operating frequencies Dynamic Growth
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Design Objectives
Challenges
VLSI Technology
Power Optimization (i.e. Management)
Low power Portable Devices
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Outline

• Objective and Background
• CMOS Power Dissipation
• CMOS Device Characteristics
• CMOS Current Mirror
• Design of Level Shifter
• Circuit Simulation
• Delay and Power Analysis
• Leakage Analysis
• Comparison Analysis
• Summary and Discussion

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CMOS Power Consumption
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Dual Supply Voltage
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Outline

• Objective and Background
• CMOS Power Dissipation
• CMOS Device Characteristics
• CMOS Current Mirror
• Design of Level Shifter
• Circuit Simulation
• Delay and Power Analysis
• Leakage Analysis
• Comparison Analysis
• Summary and Discussion

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CMOS Device Characteristics
Bode Plot
Small Signal Model
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Bandwidth Properties
Small Signal Model
Bode Plot
Unity Gain Frequency
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Outline

• Objective and Background of the Presentation
• CMOS Power Dissipation
• CMOS Device Characteristics
• CMOS Current Mirror
• Design of Level Shifter
• Circuit Simulation
• Delay and Power Analysis
• Leakage Analysis
• Comparison Analysis
• Summary and Discussion

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CMOS Current Mirror
I-V Characteristic of the Active Load Q 2
CMOS Current Mirror Circuit
Graphical Construction to Determine the Transfer
Characteristic
Transfer Characteristic
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Outline

• Objective and Background
• CMOS Power Dissipation
• CMOS Device Characteristics
• CMOS Current Mirror
• Design of Level Shifter
• Circuit Simulation
• Delay and Power Analysis
• Leakage Analysis
• Comparison Analysis
• Summary and Discussion

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Circuit Schematic for the Level Shifter
Vref
Out
Vin
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The schematic for the non-stacked output of the
buffer for better rise and fall time
Vref
Out
Vin
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Biasing Circuit
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Outline

• Objective and Background
• CMOS Power Dissipation
• CMOS Device Characteristics
• CMOS Current Mirror
• Design of Level Shifter
• Circuit Simulation
• Delay and Power Analysis
• Leakage Analysis
• Comparison Analysis
• Summary and Discussion

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Simulation
Simulation for at 250 MHz from 0.65v to 1.2v
Simulation for at 1 GHz from 0.65v to 1.2v
The simulation was done with the cadence spectre
for the 130nm process for the level shifting from
0.65v and 0.85v to the 1.2v. The duty cycle was
set at 37.5 in order to simulate the random data
type that the buffer may be used in real
application.
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Outline

• Objective and Background
• CMOS Power Dissipation
• CMOS Device Characteristics
• CMOS Current Mirror
• Design of Level Shifter
• Circuit Simulation
• Delay and Power Analysis
• Leakage Analysis
• Comparison Analysis
• Summary and Discussion

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Delay and Power Analysis
Non-stacked transistor data at 250 MHz
Non-stacked transistor data at 1 GHz
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Delay and Power Analysis
Stacked transistor data at 250 MHz
Stacked transistor data at 1 GHz
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Outline

• Objective and Background of the Presentation
• CMOS Power Dissipation
• CMOS Device Characteristics
• CMOS Current Mirror
• Design of Level Shifter through Mirror Circuit
• Circuit Simulation
• Delay and Power Analysis
• Leakage Analysis
• Comparison Analysis
• Summary and Discussion

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Leakage Analysis
Buffer off (Using PMOS switch)
Buffer off (Using NMOS switch)
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Outline

• Objective and Background of the Presentation
• CMOS Power Dissipation
• CMOS Device Characteristics
• CMOS Current Mirror
• Design of Level Shifter through Mirror Circuit
• Circuit Simulation
• Delay and Power Analysis
• Leakage Analysis
• Comparison Analysis
• Summary and Discussion

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Comparison Analysis

• M. Hamada, et al., A top-down low power design
  technique using clustered voltage scaling with
  variable supply-voltage scheme, Custom
  Integrated Circuits Conf., pp. 495498, 1998.
• H. Mahmoodi-Meimand and K. Roy, "Self-precharging
  flip-flop (SPFF) A new level converting
  flip-flop," in Proc. European Solid-State
  Circuits Conference 2002, pp.407--410, Sep. 2002.
• Peiyi Zhao, Golconda Pradeep Kumar, Archana C.
  and Magdy Bayoumi, A Double-Edge Implicit-Pulsed
  Level Convert Flip-Flop, Proceedings of the IEEE
  Computer Society Annual Symposium on VLSI
  Emerging Trends in VLSI Systems Design
  (ISVLSI04).

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Comparison Analysis

• Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic,
  Level Conversion for Dual Supply Systems, IEEE
  Transactions on VLSI Systems, Vol. 12, No. 2,
  February 2004.

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Outline

• Objective and Background of the Presentation
• CMOS Power Dissipation
• CMOS Device Characteristics
• CMOS Current Mirror
• Design of Level Shifter through Mirror Circuit
• Circuit Simulation
• Delay and Power Analysis
• Leakage Analysis
• Comparison Analysis
• Summary and Discussion

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Summary and Discussions

• Gate level power optimization with dual-supply
  voltages.
• Dual-voltage approach can achieve significant
  power saving without degrading timing
  performance of the circuit.
• A tunable level shifter has been presented with
  some power analysis.
• Thus this analog buffer could be integrated as
  part of the analog I/O
• ring as oppose to be part of the digital on chip
  thus saving on
• chip space and die size.

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Thank You
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Questions
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Current Voltage Relationship