Design Methodology

1
Design Methodology

• Alberto Sangiovanni Vincentelli
• The Edgar L. and Harold H. Buttner Chair of
  Electr. Eng. and Comp. Science
• University of California at Berkeley
• Co-Founder, Chief Technology Advisor and Board
  Member
• Cadence Design System
• Founder and Scientific Director
• PARADES (Cadence, Magneti-Marelli, ST)

2
The Changing Metrics
Performance as a Functionality Constraint (Just-i
n-Time Computing)
3
The Wireless Challenge
Radio
4
Architectural Choices
Flexibility
1/Efficiency
5
Manufacturing Cost and Design Cost

• Manufacturing costs skyrocketing
• Mask set cost alone predicted to be 1.5M to 10M
• Design cost increasing exponentially with size of
  design
• 10 Decrease in ASIC starts for 1999 w.r.t. 1998.
• Must re-consider how design is carried out
  re-use is main concern at all levels
• Platform-based Design
• (H. Chang et al., A. Ferrari and ASV, K. McMillan
  and ASV)

6
How is a platform chosen?

• Needs extensive analysis to optimize among
  competing criteria
• Performance vs. cost vs. re-use (time-to-market)
  vs. flexibility
• Millions of parts are needed to be profitable!

7
Platform-based Design

8
The Implementation OpportunityThe Radio-on-a-Chip

• DSP and control intensive
• Mixed-mode
• Combines programmable, flexible, and
  application-specific modules
• Cost and energy are the key metrics

9
The Radio-on-a-Chip Design Problem

• Multiple levels of design optimization
• The fractal nature of design
• Capturing the functionality
• Capturing the architectural choices
• Quantifying the exploration trade-offs

10
System Optimization Hierarchy
Network Level
Constraints
Constraints
Module Level
11
System Design High Leverage Paradigms

• Orthogonalization of concerns view designs along
  axes that can be dealt with independently
• Timing and functionality
• Function and Architecture
• Computation and Communication

12
System Level Design Science

• Design Methodology
• Top Down Aspect
• Orthogonalization of Concerns
• Separate Implementation from Conceptual Aspects
• Separate computation from communication
• Formalization precise unambiguous semantics
• Abstraction capture the desired system details
  (do not overspecify)
• Decomposition partitioning the system behavior
  into simpler behaviors
• Successive Refinements refine the abstraction
  level down to the implementation by filling in
  details and passing constraints
• Bottom Up Aspect
• IP Re-use (even at the algorithmic and functional
  level)
• Components of architecture from pre-existing
  library

13
Separate Behavior from Micro-architecture

• Implementation Architecture
• Hardware and Software
• Optimized Computer

• System Behavior
• Functional Specification of System.
• No notion of hardware or software!

14
Map Between Behavior from Architecture
Transport Decode Implemented as Software Task
Running on Microcontroller
15
The new approach

• Not the typical stepwise top-down refinement we
  rest on platforms!
• Explicit mapping of applications onto
  architecture components
• The higher the level of abstraction, the faster
  is the design time

16
The Essence of the Polis/Felix/VCC Approach
17
System Design High Leverage Paradigms

• Orthogonalization of concerns view designs along
  axes that can be dealt with independently
• Timing and functionality
• Function and Architecture
• Computation and Communication

18
Key Problem Ad Hoc Integration

• Bus structures inadequate for global SOC quality
  of service needs
• Excessive interdependency between blocks
• Incomplete information for front-end modeling
• Verification and test unmanageable

Conventional SOC
System Bus
DMA
CPU
DSP
Mem Ctrl.
Bridge
MPEG
C
I
O
O
Custom Interfaces
Peripheral Bus
Control Wires
19
Bottom Line Component Reuse

• The Challenge Is Not in the IP Itself, but is in
  the Component Integration Protocols
• Its not just a standard bus problem
• This is true for hardware, software, and
  so/rdware components
• Design Validation Remains the Key Bottleneck and
  is Likely to Get Even Harder

20
Communication-based Design
21
Key TechnologyCommunication Refinement
Refinement from abstract tokens to articulated
signals
2
1
System Behavior
System Architecture
Mapping
Behavior Simulation

• Value
• Design and simulate at the level of abstraction
  at which designers think (e.g. ATM cell, GSM
  frame)
• hide implementation details of the communication
  until it is required (but simulate its
  overhead!)
• refine from abstract token level down to
  implementation of interface signals
• evaluate performance trade offs of communication
  effects

3
Performance Simulation
Communication Refinement
4
Flow To Implementation
22
COSY Communication Refinement
23
Communication Synthesis
Algorithm Integration
SPW,C, C,SDL, Matlab
Does the functionally integrated design work?
Executable Functional Specification
Untimed
Architecture Performance
Are performance partitioning sufficient?
CPU, DSPBus, Memory,RTOS, HW, SW
Executable Performance Specification
Performance
Refined Integrated Design
Does the refined design work?
Clocked
Communication Refinement
Communication Pattern Synthesis
24
Key TechnologyCommunication Interface Synthesis
2
1
System Behavior
System Architecture
Synthesize communication pattern through
architecture
Mapping
Behavior Simulation

• Value
• Choose from comprehensive set of communication
  pattern
• Pattern for HW-SW, SW-HW, HW-HW and SW-SW
  communication available
• move function between HW and SW boundaries and
  re-synthesize the communication interface
• customize platform communication environment
  through JAVA scripts

3
Performance Simulation
Communication Refinement
4
Flow To Implementation
25
Digital Intercom A Design Exercise in
Communication/Component Based Design
Basestation

• Known and tested specification of limited
  complexity allows focus on architectural
  implementation methodology
• Two-chip implementation leverages separates
  between analog (RF) and digital design concerns

Mobiles
Up to 20 users per cell _at_ 64 kbit/sec per
link TDMA selected as MAC protocol
26
Two-Chip Intercom (TCI)
27
Separation of Digital Communications and Protocol
Processing

• Different tool environments require up-front
  partitioning
• Interface design critical to ensuring final
  designs work together
• Small number of interface signals
• Clearly specified behavior and constraints
• Verification relying on co-simulation

28
Performance Analysis of Base-band Processing
Produces Timing Constraints for Protocol Design
Tool Microsoft Excel
Radio Turn-aroundTime
29
Exploring the Protocol Design Space
Algorithm Design and Exploration
Algorithm Design and Exploration
Verify
Behavior
30
The Intercom Protocol Stack
Voice samples
Service Requests
User Interface Layer
Mulaw
Mulaw
UI
Transport Layer
Transport
Mac Layer
MAC
Filter
Data Link Layer
Transmit
Receive
Synchronization
Tx
_data
Rx_data
Tx
/Rx
31
Describing the Behavior
32
Formal Specification enables Verification

• Does system satisfy certain properties?
• System described in some formal mathematical
  languages (e.g. Esterel, CFSM)
• Properties written in some formal logic (e.g.
  Temporal Logic) or formal model (e.g. Esterel,
  CFSM)
• Two approaches
• Property Verification
• Invariant (only one remote can send voice data in
  any time slot)
• Response (if a remote sends a request to the base
  station, then eventually there is an
  acknowledgement)
• deadlock freedom
• Refinement Checking
• Does the (low-level) implementation conform with
  the (high-level) specification? (Do the mapped
  CFSMs function the same as the specification?)
• Example Mocha System (Henzinger, UCB)

33
Targeted Implementation Platform
34
Modeling the Architectural ComponentsThe
embedded processor

• Xtensa embedded CPU (Tensilica, Inc)
• Configurability allows designer to keep minimal
  hardware overhead
• ISA (compatible with 32 bit RISC) can be extended
  for software optimizations
• Fully synthesizable
• Complete HW/SW suite
• VCC modeling for exploration
• Requires mapping of fuzzy instructions of VCC
  processor model to real ISA
• Requires multiple models depending on memory
  configuration
• ISS simulation to validate accuracy of model

• Tensilica model in VCC The fuzzy
  instruction set

35
Modeling the Architectural ComponentsThe
Interconnect Network

• Silicon Backplane model in VCC

• Flexible bandwidth arbitration model
• TDMA slot map gives slot owner right of refusal
• Unowned/unused slots fall to round-robin
  arbitration
• Latency after slice granted is user-specified
  between 2-7 Bus Clock cycles

36
Exploring Architectural Mappings
Software Processor
ASIC Accelerators
37
Processor Utilization - Estimation
38
Summary

• System-on-a-Chip approach enables and demands
  heterogeneous implementation strategies,
  sometimes involving non-intuitive and innovative
  design platforms
• Design exploration over various fabrics and
  partitions has dramatic impact on dominant
  metrics, such as energy and cost
• It requires orthogonalization of function and
  architecture, supplemented with performance
  models (cost, time, energy)
• Architectural models for exploration in high
  demand
• This methodology holds at all levels of the
  system hierarchyThe Fractal Nature of Design