DAQ Hardware status overview R. Stokstad

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DAQ Hardware status - overviewR. Stokstad

• DOM Main Board
• Schedule (Minor)
• Design (Przybylski)
• Firmware (Stezelberger)
• Testing (Goldschmidt)
• DOR Board (Sulanke)
• Master Clock Unit (Nygren, Sulanke)
• Time Calibration, Cable measurements
• (Stokstad, Sulanke, Hardtke)

Individual presentations for the above to be in
Mons proceedings
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Rev 2 board

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Icecube DOM MB Status and Development
Schedule

• April Oct '03
• Rev 2 test and development (22 boards)
• Oct Nov 03
• Rev 3 fabrication and test (16
  boards)
• Nov 03 Mar 04
• Rev 4 fabrication and test (60
  boards)
• March June 04
• Rev 5 for deployment (420
  boards)

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Rev 3 status

• October November 03
• First 4 cards due Oct 22, 12 more to follow 5
  days after approval
• Changes from Rev 2 address memory performance at
  temperature and signal quality issues
• Testing at LBNL will include manual tests and STF
  testing
• Temp cycling of bare and loaded boards
• 65, -40degC 10 cycles
• First 4 cards to UW
• 8 cards to UW, 8 cards to LBNL

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Rev 4 plans

• November March 04
• Design modifications as indicated by Rev 3 tests
  and internal review
• Final parts selection for reliability
• 60 cards to be fabricated
• Qualification test at UW
• Longer term temperature tests
• String operation tests
• Some boards used for development at LBNL

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Rev 5 plans

• Initial production review November 03
• Based on Rev 3 and Rev 4 tests
• Earlier than usual to enable long-lead parts
  purchasing
• Production readiness review - January 04
• Based on initial Rev 4 tests
• Qualification testing
• Vendor qualifications
• Fabrication process approval

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Rev 5 Production (March June 04)

• Full production and Q/A procedures in place
• All parts as selected for reliability
• ATWD production run including qualification tests
• Any differences between Rev 4 and Rev 5 require
  formal Engineering Change Procedure and
  re-qualification testing
• Fabrication begins March 04
• Testing begins April 04
• Delivery April - June 04

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Some Changes made in Rev 3

• EPXA4 Baseline (The larger FPGA)
• Hi-Reliability Part Substitutions
• Primary Oscillator Corning (Hi-Rel 2560A-0009)
• High-Rel DC-DC Converter Power-One brand
• Low impedance Power Distrib.to SDRAM
• 2 x 12 Channel ADCs vs. 1 x 8 Channel for
  monitoring
• Q/A Tests Added to Plan Coupons on PCB
• Noise Related Layout Changes
• Fabrication procedure changes

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DOMMB Block Diagram
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Firmware

• CPLD (lowest level programmable logic device)
• Almost finished. Smallr changes needed for Rev 3
  and to make the design more robust.
• FPGA
• STF 99 Done for testing
• ConfigBoot Preliminary Version minimal boot
• IceBoot Preliminary Version normal boot
• DOMAPP 50 Done for data taking
• For software development purposes the SFT FPGA
  can be used for the ConfigBoot and the IceBoot
  FPGAs

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DOR card

• Firmware Status
• Production Status, Rev. 0
• Planned Production, Rev. 1

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DOR, DOM Readout card
96V DOM Power
Quad Cable Con.
Power Switch
Comm. DAC
Clock Time String port
Comm. ADC
PLD
Comm. Rec.
FPGA
FLASH
SRAM
JTAG
ICECUBE Meeting, Mons October 2003
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Production Status

• Rev. 0, 10 DORs running at UW 2x, Bartol 1x,
  LBNL 7x
• 20 more in production now, ready in Dec. 2003
• 4 stay at DESY, 16 go to ?

Planned Production, Rev. 1

• Redesign ready in January
• first test in Feb., production of 60 if o.k.
• 60 ready in April 2004
• 60 DORs -gt sufficient to control 480 DOMs

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DOMMB Test Plan

• Select well functioning DOM MBs (including delay
  board) suitable for integration into DOMs to be
  deployed in IceCube/IceTop.
• For boards which are not well functioning,
  provide information to aid understanding,
  debugging and fixing.
• Provide some DOMMB characterization optimum
  running parameters, etc.
• Be able to handle an expected steady state flow
  of 55 boards/week.

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Initial Tests

• Visual inspection, Power to board
• Load released firmware and software in
  dedicated setup (1 board at a time)
• Get boot prompt and tests that cannot be done
  in DOR-based setup (if any)

Burn-in

• Multiple heating and cooling cycles (65C to -40
  C) to catch infant mortality cases.
• Boards powered and some testing during burn-in
• Power cycles during burn-in
• Full operational test at the end to identify bad
  boards.

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Master Clock Unit Function

• Create and distribute stable 20 MHz source to all
  DOM Hubs in IceCube DAQ.
• DOR cards mirror MCU time, calibrate DOMs
• Link IceCube Time to GPS time .
• Provide robust real-time time verification.
• Motivation detect any error condition in less
  than 1 sec

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Master Clock Unit (MCU) Status

• Draft Requirements Document exists
• Specific Implementation proposals have been made
  by Sulanke and Przybylski.
• Plan is that Sulanke will design and fabricate
  this subsystem at DESY.

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Time Calibration Tests

• Results using a waveform template
• Cross-talk measurements
• Cable stub asymmetry results

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DOR
DOM
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Scope at DOR
Scope at DOM
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Golden Rule of Time Calibration

• One-way time 1/2 round trip time
• ONLY IF
• Symmetry in pulse generation and transmission
• Signal processing same at both ends

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DOR - DOM test
DOR - DOR test
DOR-DOR has same clock for transmitting and
receiving
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-gt linear algorithm should be OK
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DOR-DOR shifted by one clock tick 50 ns
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Dt (ns)
DV
Dt av
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Average asymmetry -1.3 ns RMS asymmetry
1.1 ns
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Runs A_02_04N B_02_04N
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Waveform Analysis
Linear fit over limited range, calculate crossing
point with pedestal
Fit range
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Round-Trip times using three methods
Note absolute scale on x-axis not adjusted
properly. OK for residuals, however.
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Waveform Analysis Summary
Using measured waveform as template and centroid
of pulse appears promising. Simple, fast,
accurate. Robust? (likely) Candidate for use in
ice.
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DOR - DOM typical resultsRound trip time rms
1 nsfor 3.4 km cable in labusing template.
(1ns in 37ms)
Boards otherwise "quiet" No transmission of data
in other twisted pair.
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Cross-talk studies

• DOR - DOM
• 3.4 km Ericsson quad on spool
• Measure round trip rms deviation with and
  without data xmission at (1 Mbit/s) in other
  twisted pair

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Cross-talk measurement results
round trip residual (rms ns)
DOM A DOM B Data transmission
on 1.5 1.5 to another quad Data
transmission on 4.4 4.7 in Ericsson quad
Runs X01_A,B X03_A,B
gt Most Cross-talk occurs in quad
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Timing error budget for clock calibration is 5 ns
total -including frequency, offset,
asymmetry. Conclude it is prudent to shut down
data transmission during RAPCAL in order to meet
timing requirement. Synchronized shutdown of
communications for calibration is now the planned
operating mode. Uses 0.5 bandwidth at 10 sec
interval Uses 5 bandwidth at 1 sec
interval (This option already envisioned in
RapCal for IceCube.)
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Cable Stub Tests

• No Stub Configurations

DOR, DOMa, and DOMb are actually one DOR card
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Cable Stub Tests

• Stub Configuration

1750 cm
3.4 km
DOR
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Stub test results (preliminary)
DOR card has single clock for all 3 channels
gt Can measure up - down asymmetry Use centroid
of positive portion of pulse

• DOMa DOMb
• asym rms asym
  rms
• 15-15 49.9 0.7 49.7 0.5
• 15-1750 49.1 0.5 49.7 0.5
• 130-1750 49.7 0.4 49.8 0.7
• (NB 1 clock tick 50 ns. Above absolute
  asymmetry is due to systematic logic error and is
  lt 1ns.)

1 2 3
These results suggest that 1.3 m cable stub does
not introduce an asymmetry with measurable effect
on time calibration.
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