Computer Architecture 2

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Computer Architecture 2

• Bryan Duggan

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Reading

• This current Section
• Computers From Logic To Architecture
• R.D. Dowsing, F.W.D Woodhams, I Marshall
• Mc Graw Hill
• ISBN 007 7095847
• Chapter 5 - The Structure of a Computer pages
  229-232
• The Principles of Computer Hardware
• Clements
• Oxford Science Publications
• ISBN 0-19-853764-6
• Chapter 5 - The Central Processing Unit
• On Number Theory
• Clements - Chapter 4
• Tocci - Chapter 2
• On Digital Logic
• Clements - Chapter 2 - Logic Gates p73 worked
  examples
• Tocci - Chapter 3 4 - Loads of worked examples
  (Ignore Karnaugh Maps)
• On Adders
• Dowsing Chapter 5 or the slides

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What is this lecture all about?

• High level concepts of PC type Computers
• The Von Neumann architecture of the CPU
• Bus
• Registers
• ALU
• Control Unit
• Register Transfer Language
• Fetch Execute Cycle
• Next Week
• Motorola 68000 Microprocessor
• Please read Chapter 6 in Clements
• Sample assembly language program
• Coming Soon!
• Memory organisation
• Memory mapped I/O and Interrupts
• Limitations to the Von Neumann Architecture

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Gates per CPU

• Vacuum tube - 1946-1957
• Transistor - 1958-1964
• Small scale integration - 1965 on
• Up to 100 devices on a chip
• Medium scale integration - to 1971
• 100-3,000 devices on a chip
• Large scale integration - 1971-1977
• 3,000 - 100,000 devices on a chip
• Very large scale integration - 1978 to date
• 100,000 - 100,000,000 devices on a chip
• Ultra large scale integration
• Over 100,000,000 devices on a chip

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Moores Law

• Increased density of components on chip
• Gordon Moore - cofounder of Intel
• Number of transistors on a chip will double every
  year
• Since 1970s development has slowed a little
• Number of transistors doubles every 18 months
• Cost of a chip has remained almost unchanged
• Higher packing density means shorter electrical
  paths, giving higher performance
• Smaller size gives increased flexibility
• Reduced power and cooling requirements
• Fewer interconnections increases reliability

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Concepts

• System Packaging
• Keep components to a minimum, problems with the
  physical interface
• Possible to fabricate all the main components on
  a single chip
• Used in high volume embedded systems
• Not in general purpose computer systems, due to
  changing requirements
• Systems assembled as a set of ICs on a PCB with
  power supply, hard disk etc.
• Technologies for linking boards together, known
  as a backpane
• PCs use a motherboard, with slots

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CPU

• Control Unit
• ALU
• Bus
• Registers

CPU Internal Bus
ALU
DataRegisters
MemoryBufferRegister
Program Counter
InstructionRegister
ControlTiming
MemoryAddressRegister
To and from external bus
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The Bus

• Main method of communicating between the
  components of a computer
• Many buses in a computer system
• Components tap into the bus to send and receive
  signals
• Only one sender must be active at any time
• Any connected device may read information
• Three different types of information
• Data
• Address
• Control

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Von-Neumann Architecture
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Registers

• Not all registers the same size
• Data or instructions need to same size as a
  memory location
• In an 8 bit Microprocessor
• Data registers are 8 bits wide
• Address registers are 16 bits wide
• Giving 64K addressable
• Memory locations need to be large enough to hold
  the highest memory location
• Intel 80806 has 20 bit memory register - Max
  addressable was 1024K (1Mb)
• Motorola 68000 has 32 bit memory register -
• Max addressable should be 232 which is 4096 Mb
• But is only 224 which 16Mb

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ALU In Detail

• ALU In Detail
• Performs arithmetic and logic operations
• Data can come from memory or input device or
  registers
• Most CPU have 8 registers. 8 bit CPUs have 1
  register called the accumulator

Data Bus
ACC
To Control Unit
ALU
Flags (CCR)
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More on the ALU

• ALU will have
• Adder same width as the registers
• Logical Tests
• Eg Logical test for 0 using a an OR gate
• Bitwise AND
• Shifting
• Comparator, euqlity, greater tha, less than, done
  using subtraction
• Integer Multiplication Division
• Floating point may be done using a FPU

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Control Unit

• To connect registers on the bus a control signal
  is required
• Everything happens on a clock cycle, like the
  computers heartbeat
• Fetches and executes instructions
• Translates macroinstructions into
  microinstrustions
• Smallest event that can take place inside a CPU
• Clocking a flip flip
• moving data from one register to another
• Clements Diagram Page 229

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Register Transfer Language

• Not to confuse you! As a shorthand for expressing
  what happens inside a CPU. Alternative
  explanations in English in Dowsing Book
• 1 or more letters followed by numbers indicates
  registers or memory location
• Square brackets means the contents of
• Left arrow means transfer
• MS means the computers memory Main Store MS(X)
  means the value in main store at memory location
  XE.g.MAR ? PCPC ? PC 1MS(20) ?
  PC

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Operation of a computer

• Known as the Fetch Execute cycle
• Fetch the next instruction from memory into the
  control unit
• Decode the instruction
• Obey the instruction
• Go back to 1

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Fetch Execute in Detail

• From Clements
• Program counter contains (points to) the address
  of the next instruction in memory
• Step 1 MAR ? PC Contents of PC are moved
  into the MAR
• MAR holds the address of a location in memory
  into which data is being written or read
• Mar now holds the contents of the PC
• Step 2 PC ? PC 1 The program counter is
  incremented
• Step 3 MBR ? MS(MAR)
• MBR takes the value of the memory location held
  in MAR
• MBR is a temporary holding place for data
  received from memory
• MBR contains the bit pattern of the instruction
  to be executed
• Step 4 IR ? MBR Instruction register takes
  value of MBR
• IR now contains the bit pattern of the
  instruction to be executed
• Divided into fields, operator and operand
• Single address instructions

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Fetch Execute in Detail

• Step 5 CU ? IR(op-code)
• The Control unit executes the instruction
• Example instructions
• P Q R
• Single accumulator
• Move Q, D0
• Add R, D0
• Move D0, P
• More complex instruction set, single clock cycle
• Add Q,R,P

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Lets look at the Add Instruction

• Step 1 MAR ? IR(address)
• MAR Takes the address part of the instruction
  register
• Step 2 MBR ? MS(MAR)
• Memory buffer takes the value of the data stored
  in memory at the address in MAR
• Step 3 ALU ? MBR, ALU ? D0
• ALU adds the contents of the MBR with the
  contents of data (accumulator) register D0
• Step 4 D0 ? ALU

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More on Operation

• Fetch cycle is always the same
• Different execution cycles depending on the
  instruction, one per instruction
• Instruction Groups
• ALU Instructions
• Move or copy instructions
• Transfer of control

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Branching/Jumping

• Branch forces the CPU to execute instruction out
  of the normal sequence
• Conditional Branch allows high level constructs
  such as IF THEN ELSE to be executed
• Based on values in the CCR
• CCR - Condition Code Register
• After the CPU executes an instruction, it updates
  the bits of the CCR
• C Carry Flay
• Z Zero Flag
• N Negative (MSB 1)
• V Overflow
• See P 237 in Clements for examples or what these
  mean

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Next Week

• Next Week, The Motorola 68000
• Organisation
• Addressing modes
• Instructions