The Design Process

1
The Design Process

• CPSC 321 Computer Architecture
• Andreas Klappenecker

2
Administrative Issues

• October 10, project deadline
• October 17, midterm exam
• Office hours
• Klappenecker TW 200pm-300pm
• Bhojwani M 1000-1100am, T 100-200pm
• Goyal W 200-400pm

3
Levels of Abstraction

• Specification
• Architectural Description
• Verilog, VHDL, ELLA or other HDLs
• Logic Design
• Gates and Registers
• Circuit Design
• Transistors sized for power and speed
• Technology mapping
• Layout

4
Levels of Abstraction

• System
• Module
• Gate
• Circuits
• Device

5
MOS Transistors

• PMOS transistor
• like a switch
• ON if gate is 1
• OFF if gate is 0
• NMOS transistor
• OFF if gate is 1
• ON if gate is 0

6
CMOS Circuits

• Simple
• Avoids difficulties
• Resilient
• Energy efficient
• Current flow only during switching time

7
Circuit Design
Layout
Layering and Fabrication
8
Hardware Description Languages

• Abstracting from circuits
• Structural description
• Specify full adder by NAND and NOR gates
• Behavioral description
• Specify full adder by functional behavior
• Improves productivity
• Natural for Computer Scientists

9
Verilog

• Structural description
• Gates, wires, input/output
• Hierarchical description possible
• (define full adder in terms of gates)
• Behavioral description
• Abstract formulation
• Functional relationships

10
Structural Verilog Example
module mux(f, a,b,sel) output f input
a,b,sel wire f1, f2 not(nsel,
sel) and(f1, a,nsel) and(f2, b, sel) or (f,
f1, f2) endmodule
b
f
a
sel
11
Behavioral Verilog Example

• module mux2(f, a,b,sel)
• output f
• input a,b,sel
• assign f (a sel) (b sel)
• endmodule

12
Another Example

• module mux2(f, a,b,sel)
• output f
• input a,b,sel
• reg f
• always _at_(a or b or sel)
• if (sel1)
• f b
• else
• f a
• endmodule

13
Synthesis

• Compilation
• Verilog code is translated into
• a network of logic gates
• Optimization
• Try to find a better solution by logic
  optimization (limited success)
• Technology mapping
• Physical design

14
Logic Gates

• and(y, a, b)
• or(y, a, b)
• not(y, a)
• xor(y, a,b)
• nand(y, a, b)

15
Modules

• module mod_name (parameters)
• input
• output
• reg
• endmodule

16
Full Adder

• module fulladd(cin, x, y, s, cout)
• input cin, x, y
• output s, cout
• assign s x y cin
• assign cout (x y) (cin x) (cin y)
• endmodule

17
Full Adder

• module fulladd(cin, x,y,s, cout)
• input cin, x, y
• output s, cout
• assign cout, s x y cin
• Endmodule
• The assign statement sets cout to MSB and s to LSB

18
Conclusions

• Verilog will be the language for our next
  projects
• Verilog compilers are freely available
• Programming in a HDL differs from software
  programming
• Higher level of abstraction allows to develop
  large circuits