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Chapter 2 Introduction of IC Fabrication

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Chapter 2. Introduction of IC Fabrication. 9/7/09. 2. Outlines ... IC Fabrication Process Module. Photolithography. Thin film growth, dep. and/or CMP. Etching ... – PowerPoint PPT presentation

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Title: Chapter 2 Introduction of IC Fabrication


1
Chapter 2Introduction of IC Fabrication
2
Outlines
  • Introduction
  • Yield
  • Cleanroom basics
  • Basic Structure of an IC Fab
  • Testing and Packaging
  • Future Trends

3
Wafer Process Flow
IC Fab
Metallization
4
Fab Cost
  • Fab cost is very high, gt 1B for 8 fab, while
    gt2B for 12 fab
  • Clean room
  • Equipment, usually gt 1M per tool
  • Materials, high purity, ultra high purity
  • Facilities
  • People, training and pay

5
Wafer Yield
6
Die Yield
7
Packaging Yield
8
Overall Yield
YT YW?YD?YC
Overall Yield determines whether a fab is making
profit or losing money
9
How Does Fab Make (Loss) Money
  • Cost
  • Wafer (8) 150/wafer
  • Processing 1200 (2/wafer/step, 600 steps)
  • Packing 5/chip
  • Sale
  • 200 chips/wafer
  • 50/chip (low-end microprocessor in 2000)

Cost of wafer, chips per wafer, and price of
chip varies, numbers here are choosing randomly
based on general information.
10
How Does a Fab Make (Loss) Money
  • 100 yield 15012001000 2350/wafer
  • 50 yield 1501200500 1850/wafer
  • 0 yield 1501200 1350/wafer
  • 100 yield 200?50 10,000/wafer
  • 50 yield 100?50 5,000/wafer
  • 0 yield 0?50 0.00/wafer
  • 100 yield 10000 - 2350 7650/wafer
  • 50 yield 5000 - 1850 3150/wafer
  • 0 yield 0 - 1350 ? 1350/wafer

Cost
Sale
Profit Margin
11
Question
  • If yield for every process step is 99, what is
    the overall processing yield after 600 process
    steps?

12
Answer
  • It equals to 99 times 99 600 times
  • 0.99600 0.0024 0.24
  • Almost no yield

13
Defects and Yield
14
Yield and Die Size
Killer Defects
Y 28/32 87.5
Y 2/6 33.3
15
Illustration of a Production Wafer
16
Illustration of a Production Wafer
Scribe Lines
Test
Structures
Dies
17
Clean Room
  • First used for surgery room to avoid bacteria
    contamination
  • Adopted in semiconductor industry in 1950
  • Smaller device needs higher grade clean room
  • Less particle, more expensive to build

18
Clean Room Class
  • Class 10 is defined as less than 10 particles
    with diameter larger than 0.5 mm per cubic foot.
  • Class 1 is defined as less than 1 such particles
    per cubic foot.
  • 0.18 mm device require higher than Class 1 grade
    clean room.

19
Effect of Particles on Masks
Particles on Mask
Stump on PR
Hole on -PR
Film
Film
Substrate
Substrate
20
Effect of Particle Contamination
Ion Beam
Dopant in PR
Particle
Photoresist
Screen Oxide
Partially Implanted Junctions
21
Cleanroom Structure
Makeup Air
Makeup Air
Fans
Equipment Area
Equipment Area
HEPA Filter
Class 1000
Class 1000
Process Tool
Process Tool
Class 1
Process Area
Return Air
Raised Floor with Grid Panels
Pump, RF and etc.
22
IC Fabrication Process Module
Thin film growth, dep. and/or CMP
Photolithography
Etching
Ion Implantation
PR Stripping
PR Stripping
RTA or Diffusion
23
Illustration of Fab Floor
Process Bays
Equipment Areas
Corridor
Service Area
Gowning Area
Sliding Doors
24
Test Results
25
Chip-Bond Structure
Microelectronics Devices and Circuits
Chip (Silicon)
Chip Backside Metallization
Melt and Condense
Solder
Substrate Metallization
Substrate (Metal or Ceramic)
26
Wire Bonding
Metal Wire
Wire Clamp
Bonding Pad
Bonding Pad
Bonding Pad
Formation of molten metal ball
Press to make contact
Head retreat
27
Wire Bonding
Lead
Bonding Pad
Bonding Pad
Lead
Lead contact with pressure and heat
Clamp closed with heat on to break the wire
28
IC Chip with Bonding Pads
Bonding Pads
29
IC Chip Packaging
30
Chip with Bumps
Bumps
31
Flip Chip Packaging
Bumps
Chip
Socket
Pins
32
Bump Contact
Bumps
Chip
Socket
Pins
33
Heating and Bumps Melt
Bumps
Chip
Socket
Pins
34
Flip Chip Packaging
Chip
Socket
Pins
35
Molding Cavity for Plastic Packaging
Molding Cavity
Top Chase
Bonding Wires
IC Chip
Lead Frame
Chip Bond Metallization
Pins
Bottom Chase
36
Ceramic Seal
Bonding Wires
IC Chip
Ceramic Cap
Cap Seal Metallization
Layer 2
Layer 2
Lead Frame, Layer 1
Pins
Chip Bond Metallization
37
Summary
  • Overall yield
  • Yield determines losing money or making profit
  • Cleanroom and cleanroom protocols
  • Process bays
  • Process, equipment, and facility areas
  • Die test, wafer thinning, die separation, chip
    packaging, and final test

38
Wet Processes
Dry
Etch, PR strip, or clean
Rinse
39
Horizontal Furnace
Wafers
Heating Coils
Quartz Tube
Gas flow
Center Zone Flat Zone
Temperature
Distance
40
Schematic of a Track Stepper Integrated System
Prep Chamber
Spin Coater
Chill Plates
Wafer
Stepper
Wafer Movement
Hot Plates
Chill Plates
Developer
41
Cluster Tool with Etch and Strip Chambers
PR Strip Chamber
PR Strip Chamber
Etch Chamber
Etch Chamber
Transfer Chamber
Robot
Loading Station
Unloading Station
42
Cluster Tool with Dielectric CVD and Etchback
Chambers
O3-TOES Chamber
Ar Sputtering Chamber
PECVD Chamber
Transfer Chamber
Robot
Loading Station
Unloading Station
43
Cluster Tool with PVD Chambers
Al?Cu Chamber
Al?Cu Chamber
Ti/TiN Chamber
Ti/TiN Chamber
Transfer Chamber
Robot
Loading Station
Unloading Station
44
Dry-in Dry-out CMP System
Wafer Loading and Standby
Polishing Pad
Post-CMP Clean
Polishing Heads
Rinse
Multi-head Polisher
Dryer and Wafer Unloading
Clean Station
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