A New Design Methodology for DSM

1
A New Design Methodology for DSM

• Abdallah Tabbara Bassam Tabbara
• Robert K. Brayton, A. Richard Newton, Kurt
  Keutzer
• GSRC NexSIS Group
• University of California at Berkeley

2
Motivation

• timing at the chip level is the main issue
• increased clock frequency
• smaller feature sizes
• global-wires
• variable inter-module interconnect lengths
• inter-module interconnect delays dominate
• bigger raw capacity that can be used by
  replication, regularity, and reuse (more global
  wires)

3
Domain SoC Design in DSM

• 200-2000 IP blocks, average size 50k gates
• dynamic range of modules sizes 1-500k gates
• types of modules hard, firm, soft
• hard layout
• firm gates aspect ratio
• soft RTL
• large number of nets 40k-100k
• pins per module 10-100
• properties
• register-bound (easier to integrate in a
  synchronous fashion)
• different area-delay trade-offs (implementations)

4
Challenges

• size issues
• bigger block sizes, aspect ratios and relative
  sizes
• number of pins, nets much bigger than blocks
• placement issues
• special design for memories?
• partitioning hard, clustering easy
• routing issues
• no channels, point to point
• busses
• many metal layers to be assigned
• timing at the chip level

5
Conventional Flows

• integration of various steps and tools
• Logic Synthesis - Physical Design
• Global - Detailed
• separation of concerns
• front end - back end
• no contract
• separation entails hundreds of iterations
• number of iterations can be proportional to
  complexity of design

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New Design Flow (NexSIS)

• minimize design iteration
• block-oriented design methodology
• planning at the early stages of the flow
• support incremental changes
• introduce retiming into the architectural
  floorplanning stage
• better handle on timing issues
• improved timing closure

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Functional Decomposition
Retiming

• provides an entry point for reused IPs
• RTL may already be well characterized
• area-delay trade-off as an important performance
  characteristic
• result is
• a set of blocks
• some area-delay trade-off estimates

• takes in lower bound constraints
• creates upper bound constraints
• reduces area of modules whenever possible
• can be made refinable and incremental
• depends on granularity of the representation
• path-based

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Placement / Routing

• initial placement/routing step
• can be a min-cut or any constructive approach
• has to be fast
• gives lower bounds on delays between modules
• placement/routing
• takes in upper bounds from retiming as
  flexibility on placement
• replaces modules resulting in better lower bound
  constraints
• objective is to reduce total chip area
• delay is reduced indirectly

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Iterations
Logic Synthesis

• placement and retiming
• until no further improvements
• may iterate many times
• very similar to
• initial min-cut partitioning
• low temperature simulated annealing
• proof of convergence criteria
• floorplanning and layout
• only a few iterations
• iteration information retained through area-delay
  trade-offs
• also proof of convergence

• assumption
• problems can be solved at the module level
• predictable for given size modules
• can be run in parallel for the different modules
• provides better estimates of area-delay
  trade-offs for subsequent iterations

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New Data Model

• Object-Oriented
• UML notation
• design management
• packages
• languages
• high-level GUI Java
• low-level C,C
• advantages
• very flexible
• disadvantages
• may be too complex

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Team Members

• Robert Brayton
• Professor
• Philip Chong
• Placement
• William Jiang
• Placement
• Routing
• Mukul Prasad
• Design Drivers
• Subarna Sinha
• MV Logic Synthesis

• Abdallah Tabbara
• Retiming
• System Archictecture
• Data Model
• SW Architecture
• Bassam Tabbara
• System Architecture
• Data Model
• Melvin Tsai
• Design Entry

12
References

• R.H.J.M. Otten, R.K. Brayton, "Planning for
  Performance", DAC, 1998.
• A. Tabbara, R.K. Brayton, A.R. Newton, "Retiming
  for DSM with Area-Delay Trade-offs and Delay
  Constraints", DAC, 1999.
• D. Sylvester, K. Keutzer, "Getting to the Bottom
  of Deep Submicron", ICCAD, 1998.
• http//www-cad.eecs.berkeley.edu/nexsis