COCO Lecture

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COCO Lecture 16Wakerly 10.1-10.4

• Read-only memory
• Static read/write memory
• Dynamic read/write memory

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Read-Only Memory (ROM)

• ROM is nonvolatile memory.
• Its contents are preserved even if no power is
  applied.

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Read-Only Memory (ROM)

• Combinational functions

• Program storage
• Boot ROM for personal computers
• Complete application storage for embedded systems.

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Two-dimensional decoding
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Larger example, 32Kx8 ROM
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Commercial ROM Types

• Fixed
• MASK ROM
• Programmable (only once)
• Programmed ROM (PROM).
• Re-programmable (multiple times)
• Erasable PROM (EPROM)
• Electrically Erasable PROM (EEPROM)

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Typical commercial ROMs
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Microprocessor EPROM application
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ROM control and I/O signals
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ROM timing
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Read/Write Memory

• a.k.a. RAM (Random Access Memory)
• Volatility
• Most RAMs lose their memory when power is removed
• NVRAM RAM battery
• Or use EEPROM
• SRAM (Static RAM)
• Memory behaves like latches or flip-flops
• DRAM (Dynamic Memory)
• Memory lasts only for a few milliseconds
• Must refresh locations by reading or writing

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SRAM
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SRAM operation

• Individual bits are D latches, not
  edge-triggered D flip-flops.
• Fewer transistors per cell.
• Implications for write operations
• Address must be stable before writing cell.
• Data must be stable before ending a write.

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SRAM array
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SRAM control lines

• Chip select
• Output enable
• Write enable

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SRAM read timing

• Similar to ROM read timing

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SRAM write timing

• Address must be stable before and after
  write-enable is asserted.
• Data is latched on trailing edge of (WE CS).

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Bidirectional data in and out pins

• Use the same data pins for reads and writes
• Especially common on wide devices
• Makes sense when used with microprocessor buses
  (also bidirectional)

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SRAM devices

• Similar to ROM packages

28-pin DIPs
32-pin DIPs
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Synchronous SRAMs

• Use latch-type SRAM cells internally
• Put registers in front of address and control
  (and maybe data) for easier interfacing with
  synchronous systems at high speeds
• E.g., Pentium cache RAMs

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Dynamic RAMs (DRAMs)
Read assert Word Line, sense Bit Line Write
assert Word Line, drive Bit Line Destructive
Read-Out Refresh Cycles needed storage decays in
ms Internal circuits read word and write
back. Higher density and cheaper than
SRAM Longer access time than SRAM
Single Transistor (and a capacitor) memory element
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DRAM read operations

• Take the word line HIGH.
• Detect whether current flows into or out of the
  cell.
• Note cell contents are destroyed by the read!
• Must write the bit value back after reading.

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DRAM write operations

• Take the word line HIGH.
• Set the bit line LOW or HIGH to store 0 or 1.
• Take the word line LOW.
• Note The stored charge for a 1 will eventually
  leak off.

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DRAM charge leakage

• Typical devices require each cell to be refreshed
  once every 4 to 64 mS.
• During suspended operation, notebook computers
  use power mainly for DRAM refresh.

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DRAM-chip internal organization
64K x 1DRAM
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RAS/CAS operation

• Row Address Strobe, Column Address Strobe
• n address bits are provided in two steps using
  n/2 pins, referenced to the falling edges of
  RAS_L and CAS_L
• Traditional method of DRAM operation for 20 years.

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DRAM read timing
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DRAM refresh timing
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DRAM write timing
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DRAM vs. SRAM

• SRAM
• Typically use six transistors per bit of storage
• Faster as it does not need to refresh
• More expensive and require more space and power
• DRAM
• Use only one transistor per bit
• Slower due to the refresh
• Higher density and more economic