OnChip Inductance Modeling and Analysis

1
On-Chip Inductance Modelingand Analysis

• Kaushik GalaVladimir ZolotovRajendran
  PandaBrian YoungJunfeng WangDavid Blaauw
• kaushik.gala_at_motorola.comMotorolaAustin, TX

2
Outline

• Overview of on-chip inductance effects
• Proposed methodology
• Impact of chip components on inductance effects
• Simulation acceleration techniques
• Conclusions

3
What is Inductance?

• Inductance is a phenomenon created by current
  traveling in a closed loop
• relates the voltage induced to the variation in
  magnetic flux
• Driver injects current into a wire which returns
  to the driver through a return path
• power and ground lines (AC ground)
• substrate
• Loop inductance is proportional to the area of
  the loop
• L mA

4
Frequency dependence

• Proximity effect
• Currents seek path of least impedance (Z R
  jwL)
• Current return paths are frequency dependent

• L reduces due to proximity effect
• R increases monotonically
• at very high frequencies, skin effect dominates,
  causing current to flow near the conductor
  surface R f 0.5

5
Frequency dependence

• Proximity effect
• Currents seek path of least impedance (Z R
  jwL)
• Current return paths are frequency dependent

• L reduces due to proximity effect
• R increases monotonically
• at very high frequencies, skin effect dominates,
  causing current to flow near the conductor
  surface R f 0.5

High frequency current flow
6
Why is Inductance Becoming Important?

• Reduction in wire resistances
• Technology scaling (thick wires, copper
  interconnect)
• Hierarchical metallurgy
• thinner wires at lower levels for density
• thicker layers at upper levels for low-skew
  (clock),low-resistance (power) and low-delay
  (signals)
• Faster clock speeds and signal transitions
• Inductive coupling can exist between two nets
  that arefar apart
• Signals travel longer distances and the return
  paths (loops) are wider
• Spread of flux is greater for larger current
  loops gt Inductance of wires becoming larger
• Resistance and inductance becoming comparable

7
Inductive Effects

• Impact on signal nets
• Oscillations, under/over shoot, inductive
  cross-talk
• Increase in signal delay, reduction in transition
  time

RC - MODEL
RLC - MODEL

• Impact on power grid
• dI/dt noise induced in the grid due to package
  inductance
• Resonance effects

8
Outline

• Inductance basics
• Proposed methodology
• PEEC model - Effect of various components
• Acceleration techniques
• Conclusions

9
Traditional Loop Inductance Approach
Step 1 Define grid, signal topology. Step 2
Define a port at the driver end and short the
receiver end of the signal line, as shown. Step
3 Compute loop impedance (Rint jwLint) at
frequency w, using an extraction tool (eg
FastHenry), independent of capacitance. Step 4
Construct a lumped circuit model using the loop
resistance and inductance with interconnect and
load capacitance.
POWER GRID SIGNAL NET TOPOLOGY
Lint
PORT DEFINITION
10
Ladder circuit model

• Approach suggested by Krauter et al. DAC 1998

• Step 1 Determine low frequency resistance Rdc ,
  inductance Ldc
• Step 2 Determine high-frequency inductance, Lhf

• Step 3 Determine cross-over frequency wc
• R(wc) wc L(wc), approximately wc Rdc / Lhf

• Step 4 Ladder synthesis for coplanar return
  paths
• equate Rdc, Ldc, Lhf and wc to determine R0, R1,
  L0 and L1

LADDER CIRCUIT MODEL
11
Loop Inductance Approach - Shortcomings

• Capacitances not modeled while extracting
  inductance.
• Device decoupling capacitance is missing,
  Interconnect cap is lumped at the end.
• Inductance of the entire loop is used for
  simulation of signal net.
• Inductance of the return path gets lumped into
  that of the conductor.
• Only the signal of interest is switched during
  analysis.
• In the power grid, many other signals will pull
  current simultaneously.
• All current injected in signal net return back to
  driver port - Single port assumption.

12
Current flow in real power grid
13
Current flow in real power grid
14
Current flow in real power grid
15
Proposed circuit model
POWER GRID SIGNAL NET TOPOLOGY AND PROPOSED
CIRCUIT MODEL

• PEEC-based model includes
• R, L, C for power grid and signal net
• Mutual inductances between all segments
• Coupling cap between adjacent metal lines
• Package inductances
• Decoupling capacitances and current sources
  between the two grids.

16
PEEC model for wire segments

• Treat each wire segment in the topology as an
  equivalent circuit
• Partial Element Equivalent Circuit (PEEC) model
• A. Ruehli IBM Journal of RD, 1972

• Resistance computed as a function of wire
  dimensions and resistivity.
• Capacitance (grounded and coupling) computed
  using formulae or 2/3D extraction tools
• Wire/Package partial inductance (self and mutual)
  computed using closed-form (analytical) formulae,
  based on Geometric Mean Distance.
• Frederick Grover, Inductance Calcultations
• C Hoer, et al. National Bureau of Standards,
  1965

17
Gate models

• Non-switching gates Panda et al, ISLPED 2000
• 80-90 of total gates
• Modeled as decoupling capacitances between the
  power and ground grids
• Capacitance is a function of input vectors and
  circuit state
• We compute the capacitance value statistically

18
Gate models

• Non-switching gates Panda et al, ISLPED 2000
• 80-90 of total gates
• Modeled as decoupling capacitances between the
  power and ground grids
• Capacitance is a function of input vectors and
  circuit state
• We compute the capacitance value statistically

19
Proposed Methodology - Advantages

• Advantages
• Makes no assumptions about current paths (no
  single-port restriction)
• Considers the effect of distributed interconnect
  cap on current distribution
• Models circuit components that significantly
  alter current loops, and hence the inductance
• decoupling capacitance of the non-switching gates
• transient switching activity in the power grid
• location of power/ground pads, along with package
  inductance
• Allows the study of shielding, explicit
  decoupling caps, etc.

20
Proposed Methodology - Issues

• Issues
• Analytical formula for partial inductance ignores
  skin effects
• Very wide metal lines need to be split into
  multiple, parallel segments
• Fully-dense L matrix leads to large simulation
  time
• Requires acceleration techniques

21
Experimental power grid topology

CROSS-SECTION VIEW
TOP VIEW

• Topology details
• Grid area - 350mm 350mm
• Power grid laid out on 3 metal layers (M3, M4,
  M5)
• Signal bus (7 lines) on uppermost metal layer
  (M5)
• Power/ground pads connected at locations A, B, C,
  D, E
• Circuit/Simulation details
• Driver/Receiver inverter size - (P-width 45mm,
  N-width 33mm)
• Input slope - 100ps, Simulation period - 500ps
• All signal lines switched from 0 to VDD

22
Loop vs. Partial inductance approach

• SPICE simulation comparison - 350mm long signal
  bus

PARTIAL INDUCTANCE MODEL
LOOP INDUCTANCE MODEL
DELAY 11.0ps, UNDERSHOOT 270 mV
DELAY 6.1ps, UNDERSHOOT 140 mV
23
Loop vs. Partial inductance approach

• SPICE simulation comparison - 700mm long signal
  bus

PARTIAL INDUCTANCE MODEL
LOOP INDUCTANCE MODEL
DELAY 13.0ps, UNDERSHOOT 210 mV
DELAY 19.0ps, UNDERSHOOT 410 mV
24
Outline

• Inductance basics
• Proposed methodology
• PEEC model - Effect of various components
• Acceleration techniques
• Conclusions

25
Effect of device caps, current sources

• Device caps reduce oscillations

No Decoupling Caps
Original
DELAY 6.1ps, UNDERSHOOT 140 mV
DELAY 4.5ps, UNDERSHOOT 157 mV
26
Effect of device caps, current sources

• Device caps reduce oscillations
• Current sources reduce undershoot

No Decoupling Caps
Original
DELAY 6.1ps, UNDERSHOOT 140 mV
DELAY 4.5ps, UNDERSHOOT 157 mV
No current sources DELAY 6.5ps, UNDERSHOOT
165 mV
27
Effect of pad inductance
Pad inductance significantly changes absolute
voltages
With Pad Inductance - Absolute voltages
Without pad inductance
DELAY 6.1ps, UNDERSHOOT 140 mV
DELAY 6.0ps, UNDERSHOOT 240 mV
28
Effect of pad inductance
Pad inductance significantly changes absolute
voltages Relative voltages are not greatly
affected
With Pad Inductance - Relative voltages
Without pad inductance
DELAY 6.0ps, UNDERSHOOT 120 mV
DELAY 6.1ps, UNDERSHOOT 140 mV
29
Effect of pad location
Pad locations change current return paths and
hence inductance.
1 power pad at C, 1 ground pad at D
2 power pads at A and C, 2 ground pad at B and D
DELAY 6.3ps, UNDERSHOOT 160mV
30
Outline

• Inductance basics
• Proposed methodology
• PEEC model - Effect of various components
• Acceleration techniques
• Conclusions

31
Acceleration techniques

• Model Order Reduction
• PRIMA, Odabasioglu et al. ICCAD 97
• Guaranteed passivity of reduced order model
• Increase in number of ports and number of
  moments/port leads to large run-time for the
  reduction algorithm
• Sparsification
• Drop small entries from the partial inductance
  matrix
• Can lead to a non-positive definite matrix gt new
  system generates energy
• No control/measure of loss in accuracy
• Krauter et al. ICCAD 95
• Shift and truncate
• Remove couplings between wires with large
  separation
• Better accuracy, guaranteed passive
• Ken Shepard et al. CICC 99
• Halos around critical nets define dense coupled
  clusters

32
Proposed Acceleration - PRIMA

• 1. Define ports at VDD/GND pads, driver to signal
  connections,and driver to rail connections
• 2. Compute multi-port reduced order model for the
  linear (RLC) circuit
• 3. Combine with non-linear devices, connected to
  appropriate ports
• 4. Simulate the reduced system in SPICE.

33
Proposed Acceleration - Sparsification

• Since the partial inductance matrix is dense, the
  computation of the reduced order model is
  expensive. Hence, we use simple block diagonal
  partitioning to obtain a sparse L matrix.
• Guaranteed passive
• Loss of accuracy
• Experiments show the error to be lt 5 for most
  cases

34
Acceleration results
35
Acceleration results
36
Conclusions

• Presented common inductance effects for on-chip
  structures
• Discussed traditional loop-inductance based model
• Proposed a PEEC based inductance model
• includes device decoupling capacitance, switching
  current,pad inductance
• compared with traditional loop based approach
• studied effect of a number of model elements
• Discussed methods for accelerating analysis
• Future Work
• Enhance the model order reduction algorithm with
  fast multipole acceleration, to speed up
  processing ofdense matrices.