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A sample Incomplete C Program

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4) Comments are preceded by # /; and are ignored during Assembly translation. ... Data Memory Segment or will contain an 8/ 16/32Bit Machine ... – PowerPoint PPT presentation

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Title: A sample Incomplete C Program


1
A sample Incomplete C Program
  • int AI_Fib 10, I_n 4, AI_Arg105,7,10,13
  • int main ( )
  • //begin main
  • int IF_Fibonacci (int) I_Idx
  • for (I_Idx0 I_Idx ltI_n I_Idx)
  • //begin for 1
  • AI_Fib I_IdxIF_Fibonacci(AI_ArgI_Idx
    )
  • printf ( Fib (d) d\n, AI_ArgI_Idx
  • AI_FibI_Idx)
  • //end for 1
  • //end main

2
The Pentium Integer Registers
3
Common Conventions Adopted
  • 1)  Constant values are either qualified as
    relevant types quantity and preceded by 0 as well
    as suffixed by the type specifying letter H
    (Hex) or D (Decimal) e.g. 020 H ? 20 Hex, 030 D
    ? 30 Decimal OR specified using relevant pseudo
    Op Code.
  •    2) A GPR/CPU Register is preceded by a
    special character / .
  •    3) A Memory location is either directly
    Addressed via a Symbol or by the specified
    addressing modes To be Illustrated Later
  • 4) Comments are preceded by / and are
    ignored during Assembly translation.
  • 5) The relative ordering of the Operands in
    an instruction may vary from assembler to
    assembler even for the same CPU.

4
The Compiled Pentium Assembly Code 1The
Assembler Directives (Pseudo Ops)
  • .file main.c The file
    Directive/ Pseudo Op
  • .globl I_n Global
    Symbol Directive
  • .data Data
    Segment STARTS
  • .align 4 Align with
    4 Byte Boundary
  • .type I_n , _at_object Details of I_n
  • .size I_n, 4 I_n Size is 4
    Bytes
  • I_n Label I_n The
    Symbolic Pointer
  • .long 4 Initial Value 4
    of 4 Byte Size

5
The Compiled Pentium Assembly Code 2The
Assembler Directives (Pseudo Ops)
  • .globl AI_Arg Another Global
    Object
  • .align 32 Align with 32
    Byte Boundary
  • .type AI_Arg,_at_object Details of AI_Arg
  • .size Ai_Arg,40 Size 4 10 40
    Bytes
  • AI_Arg Label The Symbolic Base
    Pointer
  • .long 5 Initial Value of
    AI_Arg 0
  • .long 7 Initial Value of
    AI_Arg 1
  • .long 10 Initial Value of
    AI_Arg 2
  • .long 13 Initial Value of
    AI_Arg 3
  • .zero 24 Remaining 24 Bytes
    initialized to 0

6
The Compiled Pentium Assembly Code 2The
Assembler Directives (Pseudo Ops)
  • .LC0 Label LC0 ,
    Symbolic Pointer
  • .string fib(d) d \n
    Format Specification
  • .text Code Segment
    Starts Here
  • .align 2 Align in 2 Byte
    Boundary Pseudo Op
  • .globl main Global Symbol main
    Pseudo Op
  • .type main,_at_function Function
    main Pseudo Op
  • main Instruction Label Entry
    Point
  • pushl ebp PUSH CPU register ebp in
    User Stack
  • esp ? esp
    MINUS 4
  • Mesp ? ebp
    Little Endian Conven.

7
The Compiled Pentium Assembly Code - 4
  • pushl ebx PUSH CPU register ebx
    in User Stack
  • esp ? esp
    MINUS 4
  • Mesp ? ebx
    Little Endian Conven.
  • subl 4, esp esp ? esp MINUS 4
    (Decimal)
  • Create
    4 Byte Space in Stack
  • andl -16,esp esp ? esp -16
    (Decimal)
  • Align
    Stack Pointer in 16 Bit Bound
  • movl 0,eax eax ? 0 (Decimal)
  • subl eax, esp esp ? esp MINUS eax
    Set Flags ?

8
The Compiled Pentium Assembly Code - 5
  • movl 0 , -8(ebp) M ebp-8 ? Decimal
    0
  • Local
    Variable I_Idx ?0
  • 32 bit 2s Complement Value in Little Endian
    Convention
  • .L2 Label
  • movl 8(ebp) , eax eax ? M ebp 8
    (I_Idx)
  • cmpl I_n, eax Compare I_n with
    I_Idx
  • jl L5 if I_Idx lt
    I_n go to label .L5
  • jmp L3 Otherwise (I_Idx gtI_n) go to
    label .L3 (EXIT)

9
The Compiled Pentium Assembly Code - 6
  • .L5 Label L5
  • movl 8(ebp), ebx ebx ? Mebp-4
    I_Idx
  • subl 12 , esp esp ? esp MINUS 12
    (Decimal)
  • Create 12
    Byte Stack Space for Parameters
  • movl -8(ebp), eax eax ? Mebp-4
    I_Idx
  • pushl AI_Arg(,eax, 4)
  • Push MAI_Arg 4 eax (Actually
    I_Idx)
  • Push AI_Arg0 the First Parameter
  • call IF_Fibonacci User Function Call
  • addl 16, esp esp ? esp PLUS 16
    (Decimal) Reclaim
  • Stack Space used
    for Fibbonaci Function

10
The Compiled Pentium Assembly Code - 7
  • movl eax, IF_Fibonacci ( , ebx, 4)
  • Returned Value is in eax Now IF_Fibonacci
    I_Idx ? This Value
  • M IF_Fibonacci4ebx (actually I_Idx)
    ? eax
  • subl 4 , esp esp ? esp MINUS 4 (Decimal)
  • Create 4 Byte Stack
    Space for Storing Function Value
  • movl -8(ebp), eax eax ? Mebp-4 I_Idx
  • pushl IF_Fibonacci( ,eax, 4)
  • Push M IF_Fibonacci 4 eax
    (Actually I_Idx)
  • Push IF_Fibonacci I_Idx
  • movl -8(ebp), eax eax ? Mebp-4 I_Idx
  • pushl AI_Arg(,eax, 4)
  • Push MAI_Arg 4 eax (Actually
    I_Idx) AI_Arg0
  • pushl .LC0 Push the address of the
    Format String
  • call printf System Function Call

11
The Compiled Pentium Assembly Code - 8
  • addl 16, esp Reclaim Stack Space used for
    printf
  • leal -8(ebp) , eax
  • eax ? Address obtd by ebp MINUS 8 I_Idx
  • incl (eax) Increment the Memory Location
    Pointed to
  • by the eax I.e. I_Idx
  • jmp .L2 Continue LOOPING
  • .L3 Loop Exit Point
  • movl -4(ebp) , ebx ebx ? M ebp 4
    Restore old
  • leave Clear Stack esp ? ebp
  • ret

12
Basic Features of Assembly Language (Generated by
the Compiler after translating the HLL / Source
Code)
  •    A language, which is machine/CPU dependent.
  •    The humans can perceive it too.
  •   Composed of mnemonic Op-Codes (small English
  • like words specifying the Operation to be
    performed)
  • Labels Operand Addresses.
  •   Has got two (2) distinct types of OP-Codes
    namely
  • a)    Executable Machine OP-Codes.
  • b) Assembler Directives (Non Executable/
  • Assembler Dependent only) Pseudo
    OP-Codes.

13
Typical Format of Assembly Instruction(
Assembler Dependent )
  • ltSymbolic Labelgt optional useful for usage as
    Target Operand Address of Branching / Jump
    Instructions or Symbolic Address Pointer
  • ltMnemonic Machine OP Codegt ltOperand ? 1 Addressgt,
  • ltOperand ? 2 Addressgt, , ltOperand ? n Addressgt
  • Number of Operand Addresses in an instruction(n)
    may vary from 0 to 4 to be illustrated later.
    Here it is 2 . The Relative Ordering of Operands
    ( Source , Destination for 2 Operands , Result ,
    Source 1 , Source 2 for 3 Operands ) is also
    assembler dependent.

14
Typical Format of Assembly Instruction(
Assembler Dependent ) Example
  • .L3
  • movl -4(ebp) , ebx
  • Label .L3
  • Mnemonic Op Code movl Data Movement
  • Source Operand -4(ebp) Based Offset Addr.
  • Destination Operand ebx Register Direct Addr.

15
Basic Op Code Types in an Instruction Set
Architecture (ISA) - 1
  • Data Movement
  • Source
    Destination
  • CPU Register Memory /
    Peripheral Register
  • Memory/Peripheral Register CPU
    Register
  • CPU Register
    CPU Register
  • Immediate Data
    CPU Register
  • Immediate Data
    Memory / Peripheral

16
Basic Op Code Types in an Instruction Set
Architecture (ISA) - 2
  • Data Processing
  • Operand 1 Operand2
    Result Destination
  • CPU Register Memory /
    Peripheral Register
  • Memory/Peripheral Register CPU
    Register
  • CPU Register
    CPU Register
  • Immediate Data
    CPU Register
  • Immediate Data
    Memory / Peripheral

17
Basic Op Code Types in an Instruction Set
Architecture (ISA) - 3
  • Control Flow
  • Op Code Target Address Memory

18
Operand Addresses in the Instruction Set
Architecture (ISA) - 1
  • A. Constants/ Immediate Data Binary Integers of
    various sizes (signed /unsigned) . Sign depends
    on the Interpretation. Usually Hexadecimal (Hex)
    notation is used for compactness. However we
    shall be using decimal , the underlying
    conversion will convert it into binary /hex.
  • Typical sizes Byte 1 Character , Word
    2 Bytes , Double Word/ Long 4 Bytes , Quad
    Word 8 Bytes

19
Operand Addresses in the Instruction Set
Architecture (ISA) - 2
  • B. CPU Registers
  • 1) General Purpose Registers GPRs can
    be used to store Data , Address, Result of
    Computation. Usually programmer accessible partly
    / as a whole.
  • 2) Special Purpose Registers Specific
    Purpose of usage like Instruction Pointer, Stack
    Pointer, Segment Registers Restricted
    accessibility.
  • 3) Condition Flags Stores status of
    computation like ZERO Flag , SIGN Flag, CARRY
    Flag. Useful in conditional Control Flow
    Instructions.

20
Operand Addresses in the Instruction Set
Architecture (ISA) - 3
  • C. Main Memory / RAM / RWM Locations
  • A location ? ( Address , Data Content ).
  • There are several ways to address a memory
    location depending on the Addressing Modes as
    provided by the CPU. This will be illustrated in
    due course. All memory accesses happens through
    Cache Memories ( is ignored for the time being).
  • D. Stack LIFO Memory Grows from Higher
    Address towards lower Address. Accessed via some
    special purpose registers termed as Stack
    Pointer. Useful for passing parameters , storage
    of activation records . Will be illustrated in
    due course.

21
Machine Language Features
  • 1)    Obtained by translating an assembly
    language program by an Assembler
  • 2) Everything i.e. Machine OP Codes, Operands as
    well as constant values are represented in Binary
    Form i.e. strings of 1s 0s or in Hex notation
    (for compactness sake).
  • 3)   A language that can be directly interpreted
    by the machine but difficult to interpret by the
    humans
  • e.g.
  • movl esp, ebp ? ebp ? esp gt 1000 1001
    1110 0101

  • ? 89E5

22
Machine Language Conventions
  • 1)  Each Memory Location 8 bit wide
  • i.e. 1 byte wide (2 Hex digits)
  •    2) Each Memory Address 32 bit wide
  • i.e. 4 byte long 8 Hex digits.
  • a) Hence any memory variable/symbolic
    operand will be
  • represented by 8 Hex digits
  • b) Any statement symbolic label will
    translate to 8 Hex digits.
  • c) Any memory location having a 32 bit
    address will either
  • contain 8 bit data (Operand Value)
    belonging
  • Data Memory Segment or will contain an
    8/ 16/32Bit Machine
  • Op-Code Program Memory / Code Segment

23
Assembly Machine Code ( List File) - 1
  • Location Machine Code
    Symbol/Label Directive Value
  • (in HEX)

    .data


  • .align 4

  • .type
    I_n,_at_object

  • .size I_n,4

  • I_n
  • 0000 04000000
    .long 4

  • .globl
    AI_Arg
  • 0004 00000000
    .align 32

  • .type
    AI_Arg,_at_object

  • .size
    AI_Arg, 40

  • AI_Arg
  • 0020 05000000
    .long 5
  • 0024 07000000
    .long 7




24
Assembly Machine Code ( List File) - 2
  • Location Machine Code
    Symbol/Label Directive Value
  • (in HEX)
  • 0020 0A000000
    .long 10
  • 0024 0D000000
    .long 13
  • 0030 00000000
    .zero 24

  • 00000000

  • 00000000

  • 00000000

  • 00000000


  • .section .rodata

  • .LC0
  • 0000 66696228
    .string
    fib(d)d\n

  • 25642920

  • 3D202564
  • 0A00



25
Assembly Machine Code ( List File) - 3
  • Location Machine Code
    Symbol/Label Directive Value
  • (in HEX)

    .text


  • .align 2


  • .globl main

  • .type
    main,_at_function

  • main START of Execution
  • 0000 55
    pushl ebp
  • 0001 89E5
    movl esp,ebp
  • 0003 53
    pushl ebx
  • 0004 83EC04
    subl 4,esp
  • 0007 83E4F0
    andl -16.esp
  • 000a B800000000
    movl 0, eax
  • 000f 29C4
    subl eax,esp
  • 0011 C745f800
    movl 0,-8(ebp)
  • 000000




26
Assembly Machine Code ( List File) - 4
  • Location Machine Code
    Symbol/Label Directive Value
  • (in HEX)

  • .L2
  • 0018 8B45F8
    movl -8(ebp), eax
  • 001B 3B050000
    cmpl I_n, eax
  • 0000
  • 0021 7C02
    jl .L5

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