Network Processor and Its Applications

1
Network Processor and Its Applications

• Yan Luo yluo_at_cs.ucr.edu
• Chris Baron cbaron_at_cs.ucr.edu

2
Outline

• Overview of the network processors
• The NP market
• IXP2400/2800
• High Performance Networking with IXP
• Initial Design
• To-do list

3
What the Internet Needs?
ASIC (large, expensive to develop, not flexible)
Increasing Huge Amount of Packets Routing,
Packet Classification, Encryption, QoS, New
Applications and Protocols, etc..

• High processing power
• Support wire speed
• Programmable
• Scalable
• Specially for network applications

General Purpose RISC (not capable enough)
4
NP market
5
Typical NP Architecture
6
Some commercial NP products
Wait, see Tilman Wolfs slides
7
Intel IXP2400
See another file
8
Cluster Architecture

• Myrinet/Quadrics/etc. provide their own protocol
  (much simpler than TCP/IP)
• Limited to LAN
• Cost (Ethernet is cheap and standard)
• Future networks require high-speeds

9
System Architecture
Pentium
DRAM
850E
PCI

I21555 PCI bridge
PCI Unit
ME
XScale
ME
SDRAM 256MB
SRAM 8MB
ENP2611
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Memory Spaces

• Virtual memory
• Physical memory
• PCI space memory
• Primary side
• Secondary side
• Bridge translates from one side to the other

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Memory Mapping
12
PCI Configuration
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Bridge Configuration

• Host-gtIXP2400 setup at boot time
• 00000000-0009ffff System RAM
• 000a0000-000bffff Video RAM area
• 000c0000-000c7fff Video ROM
• 000f0000-000fffff System ROM
• 00100000-1ff76fff System RAM
• 00100000-0027588a Kernel code
• 0027588b-002d90ff Kernel data
• 1ff77000-1ff78fff ACPI Non-volatile Storage
• 1ff79000-1fffffff reserved
• 81882000-82882000 Bigphysarea
• d0000000-efffffff PCI Bus 02
• d0000000-dfffffff PCI device 8086b555 (Intel
  Corp.)
• eff00000-efffffff PCI device 8086b555 (Intel
  Corp.)
• f0000000-f7ffffff Intel Corp. 82850 850
  (Tehama) Chipset Host Bridge (MCH)
• f8000000-fbffffff PCI Bus 01
• f8000000-fbffffff ATI Technologies Inc Rage
  128 Pro TF
• fec00000-fec0ffff reserved
• fee00000-fee0ffff reserved

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What does the device driver(s) need to do?

• Identify Device
• Pci_table contains vendorid, deviceid, etc.
• Identify Device Resources
• pci_resource_start(dev, i)
• pci_resource_end(dev, i)
• Primary side maps secondary registers and SDRAM
• Secondary side maps hosts SDRAM (mempool)
• Request Device Resources
• request_mem_region(start, end)

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What does the device driver(s) need to do?

• Allocate Device Resources
• ioremap(start_phys, size)
• make_proc_entry(start_virt, size)
• Allocate Host Resources
• bigphysarea_alloc_pages(size)

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Bridge Configuration

• Direct Address Translation (DAT)
• Stick in figure here
• Alert secondary side off required offset (since
  the mempool may not start on a perfect boundary)
• Lookup Table (LUT)
• Bridge has 64 entries in the LUT
• Each entry is configurable up to 32MB

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Bridge Configuration

• Input address divided into three parts
• Bit 31 base address
• Bits 30-25 lookup table index (26 64)
• Bits 24-0 offset (225 32MB)
• Highest 7 bits of LUT entry indexed by bits 30-25
  of input address, concatenated with bits 24-0 of
  input address
• This is where we are having problems

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Host-gtIXP2400 Transfer

• DMA or PIO?
• PIO provides zero-copy through remap_page_range()
• DMA requires an ioctl() call
• Copying data
• Standard memcpy() (8-bits)
• Memcpy32() (32-bits)
• memcpy(64() (64-bits using MMX registers)
• Utilizing write-combining

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IXP2400-gtHost Transfer

• DMA or PIO?
• DMA is required
• Give both channels to microengines
• Prefers 64-byte data transfers

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DMA Descriptor
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M-VIA
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Basic Theory of Operation

• Polling
• Host application places data into secondary SDRAM
  region
• Host application alerts secondary of data being
  placed and its location through mailbox register
• Host application polls receive mailbox register
  until it is updated by secondary side

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Basic Theory of Operation

• Interrupt
• Secondary must poll
• Secondary triggers interrupt on host side to
  alert host of new data
• When do you interrupt (how often)?
• Who provides the network interface?
• Speed
• Security

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END
26
Network Architecture and Applications

• Introduction to networking
• IP packet structure
• Control and data planes
• Traditional applications
• IPv4 routing, classification etc.
• New applications
• URL-based switching,transcoding, etc.

27
OSI Network Architecture
Source Network Processor Tutorial in Micro 34 -
Mangione-Smith Memik
28
TCP/IP Model
Source Network Processor Tutorial in Micro 34 -
Mangione-Smith Memik

• ISO OSI (Open Systems Interconnection) not fully
  implemented
• Presentation and Session layers not present in
  TCP/IP

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TCP/IP packet
Source Network Processor Tutorial in Micro 34 -
Mangione-Smith Memik
30
TCP/IP packet
Source Network Processor Tutorial in Micro 34 -
Mangione-Smith Memik
31
TCP/IP packet
APP. DATA
TCP
IP
MAC
MAC
Source Network Processor Tutorial in Micro 34 -
Mangione-Smith Memik
32
Application Categorization

• Control-Plane tasks
• Less time-critical
• Control and management of device operation
• Table maintenance, port states, etc.
• Data-Plane tasks
• Operations occurring real-time on packet path
• Core device operations
• Receive, process and transmit packets

Source Network Processor Tutorial in Micro 34 -
Mangione-Smith Memik
33
Processing Tasks
Source Network Processor Tutorial in Micro 34 -
Mangione-Smith Memik
34
Data Plane Tasks

• Media Access Control
• Low-level protocol implementation
• Ethernet, SONET framing, ATM cell processing,
  etc.
• Data Parsing
• Parsing cell or packet headers for address or
  protocol information
• Classification
• Identify packet against a criteria (filtering /
  forwarding decision, QoS, accounting, etc.)
• Data Transformation
• Transformation of packet data between protocols
• Traffic Management
• Queuing, scheduling and policing packet data

Source Network Processor Tutorial in Micro 34 -
Mangione-Smith Memik
35
Network Processor Applications

• Routing table lookup
• Determine the next hop for incoming packets
• Packet Classification
• classify packets using header fields against a
  set of rules
• URL-based Switching
• Distribute HTTP requests based on URLs.
• Transcoding
• Encryption/Decryption, intrusion detection,
  firewall, access control checking,
  denial-of-service

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IPv4 Routing
P
P
P
B
A
Router
C

• Routers determine next hop and forward packets

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Trie-based Routing Table Lookup
rt_ptr
trie_ptr
0
Trie block
Next hop 3
Next hop 4
15
Next hop 1
Next hop 2

• Trie block keeps pointers to route entry and
  other trie blocks
• Destination IP address bits are examined group by
  group (4-bit)

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Example
rt_ptr
trie_ptr
0
Next hop 3
Next hop 4
15
Next hop 1
Next hop 2
Packet destination IP address 0x13fe2233
(0001,0011,1111,1110,)
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IP Lookups using Multi-way Multi-column Search
Illustration of the idea with 6-bit
address Prefixes 1 101 10101
1 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0
101011 101110 111110
Binary search does not work with variable length
strings.

• end up far away from the matching prefix
• Multiple addresses that match to different
  prefix, end up in the same region

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Multi-way multi-column search
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Packet Classification

• Routers are required to distinguish packets for
• Flow identification
• Fair sharing of bandwidth
• QoS
• Security
• Accounting, billing
• etc
• Packets are classified by rules
• Src IP, Dest IP, src port , dest port etc
• Classification Algorithm Metrics
• Search speed
• Storage cost
• Scalability
• Updates
• Etc.

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Classification Hierarchical tries
Pankaj Gupta and Nick McKeown,"Algorithms for
Packet Classification", IEEE Network Special
Issue, March/April 2001, vol. 15, no. 2, pp
24-32.

• Extension of the one dimensional radix trie
• Construct trie recursively
• Contruct F1-trie on the set of prefix Rj1
• For each prefix p in F1-trie, we recursively
  construct (d-1) dimensional hierarchical trie on
  rules where RjRj1p

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Classification Bitmap-intersection
The set of rules S that a packet matches is the
intersection of d sets, Si Where Si is the set of
rules that match the packet in the i-th dimension
alone.
0
0
Pankaj Gupta and Nick McKeown,"Algorithms for
Packet Classification", IEEE Network Special
Issue, March/April 2001, vol. 15, no. 2, pp
24-32.
44
URL-based switching
www.yahoo.com
Internet
Image Server
APP. DATA
TCP
IP
Application Server
Switch
GET /cgi-bin/form HTTP/1.1 Host www.yahoo.com

• Increase efficiency
• Tasks
• Traverse the packet data (request) for each
  arriving packet and classify it
• Contains .jpg -gt to image server
• Contains cgi-bin/ -gt to application server

HTML Server
Source Network Processor Tutorial in Micro 34 -
Mangione-Smith Memik
45
Transcoders

• Two important requirements
• If the receiver is not capable of interpreting
  the stored data (multimedia transcoders)
• wireless receivers, hand-held devices, etc.
• Compression for bandwidth and storage efficiency

Source Network Processor Tutorial in Micro 34 -
Mangione-Smith Memik
46
Summary

• NP is developing very fast and is a hot research
  area
• Multithreaded NP Architectures provide tremendous
  packet processing capability
• NP can be applied in various network layers and
  applications
• Traditional apps forwarding, classification
• Advanced apps transcoding, URL-based switching,
  security etc.
• New apps

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Reference

• Pankaj Gupta and Nick McKeown,"Algorithms for
  Packet Classification", IEEE Network Special
  Issue, March/April 2001, vol. 15, no. 2, pp
  24-32.
• Bill Mangione-Smith, Gokhan Memik, Network
  Processing Applications, Architectures and
  Examples Tutorial at Micro 34, Dec. 2001
• B. Lampson, V. Srinivasan and G. Varghese, IP
  Lookups using Multiway and Multicolumn Search,
  IEEE/ACM Transactions on Networking, August 1,
  1997
• Intel IXP1200 Network Processor Family -
  Development Tools User's Guide, Intel

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Why are Network Processors useful?

• Flexible but fast
• Heat dissipation
• Opteron 248 2.2Ghz CPU with 1GB RAM and 10Gb/s
  Ethernet Card
• CPU maxed out at 5Gb/s
• With TOE, achieved 7.4 Gb/s (PCI-X limit) with lt
  50 of CPU utilization