Low Power, Fast, Robust Clock Signal Distribution

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Low Power, Fast, RobustClock Signal Distribution
Clock Source
Block 1
Block 2
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• 5/8/2002

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Traditional Clock Tree Design
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Early clock trees

• Early trees used wire width adjustment to balance
  loads to reduce skew

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Buffers

• By placing buffers intelligently, power actually
  reduced.

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Our first try

• Process variation, unbalanced loads, inter-line
  coupling, inductive effects

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Our automated CT generator

• Balanced tree Process variation, unbalanced
  loads, inter-line coupling, inductive effects

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Chip Slide

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Single Block

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Tests ObservationsResults

• Runtime
• Approach 2 Saves 20
• X16 Saves 17

• Power
• X16 Saves 10 - 14

• Skew Process Variation
• X16 Better by 50

Hours
mW
ns
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Tests ObservationsBuffer Area

• Buffer Area
• X8 gt X16 gt X32

70 21
DB Units
23 14.5
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Cool Delay Graphs
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Advantages

• Quick
• Brainless
• Tool approximations basically met simulation
  results and actual performance
• Works well on small designs

Disadvantages

• Lower limit on skew and therefore frequency
• Bad results for medium to large designs
• Not optimized for power minimization

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Design
Ease of Design
Minimal skew
Minimal power
H-Tree
Small regions
?
Design dependent
Design independent
Grid
Giant signals
Binary tree
?
Multi-VDD
Sloooowwwww systems (adiabatic systems, sine wave
clock) High VT systems
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Filling those boxes

• Traditional trees to distribute clock signals can
  only get worse as frequency and chip size
  increase.
• Itd be nice if we could use some properties of
  the high frequency and thin lines of recent
  technologies in some way to benefit clock
  distribution.
• Higher frequency and longer lines introduce
  inductive effects and with parasitic capacitance,
  a transmission line model and/or resonant
  circuits comes to mind.

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Ideas

• To reduce skew Somehow link clock tree as in a
  grid.
• Problem Power hungry as present grids are
  designed (Alpha 21264).
• To reduce power Use resonance to propagate
  signals through grid instead of exclusively
  driving from external sources.
• Problem How do you do that?

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Resonant Drivers

• Blip drivers generate rounded pulses.
• The all-resonant driver requires no input signal
  but still generates a rounded signal.
• Superimposing a finite number of signal harmonics
  gives squarer wave. But constant current hurts
  power consumption performance.

W. C. Athas, Theory and Practical Implementation
of Harmonic Resonant Rail Driver, 2001 ISLPED
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Voltage Pulse-fed Harmonic Resonant Rail Driver

• Using a voltage pulse-fed systems adjusts swing
  from -Vdd to Vdd, to 0 to Vdd as well as
  reducing power consumption. The R between the
  input and output removes high frequency
  components.

W. C. Athas, Theory and Practical Implementation
of Harmonic Resonant Rail Driver, 2001 ISLPED
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Blip Grid
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Blip Grid
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Blip Grid
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Hows this become a clock Distribution network?

• Challenge The signal needs to be propagated and
  locked to synchronize signal across region.
• Problems with using these drivers
• Pulse-fed, square-wave generating circuits too
  complicated to use in propagation
• All-resonant blip driver has rounded pulses
  Hurts skew and power.
• Area hungry

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Design
Ease of Design
Minimal skew
Minimal power
H-Tree
Small regions
?
Design dependent
Design independent
Grid
Grid?
Giant signals
H-Tree
Binary tree
?
Multi-VDD
Sloooowwwww systems (adiabatic systems, sine wave
clock) High VT systems
Binary tree
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Other Ideas Using Transmission Line properties to
Reduce Power

• For L gt ?/4 at high frequencies, swing at output
  of A is reduced. Power can be reduced at
  frequencies gt 3GHz. 66 at 5GHz in article read.
  (Only appropriate for global clock network).

M. Mizuno, On-chip Multi-GHz Clocking with
Transmission Lines, 2000 IEEE ISSCC
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Other Ideas Using Transmission Line properties to
Reduce Power

• ??? Local clocking networks have large
  capacitance which can cause degradation of rise
  time caused by Z0CL. A low Z0 is not appropriate
  for long lines.

M. Mizuno, On-chip Multi-GHz Clocking with
Transmission Lines, 2000 IEEE ISSCC
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Design
Ease of Design
Minimal skew
Minimal power
H-Tree
Small regions
?
Design dependent
Design independent
Grid
Giant signals
H-Tree
Binary tree
?
Multi-VDD
Sloooowwwww systems (adiabatic systems, sine wave
clock) High VT systems
Binary tree
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New Clock Signal Distribution Technology Claims

• Name Rotary Traveling-Wave Oscillator Arrays
• Clock Distribution Claims
• Gigahertz-rate
• Multi-phase (3600)
• Square wave signal
• Low jitter
• Scalable
• Potential for low power, low-skew, no need for
  clock domains.

J. Wood, T. C. Edwards, Rotary Traveling-wave
Oscillator Arrays A New Clock Technology, IEEE
Journal of Solid-State Circuits, November 2001,
Vol. 36, No. 11
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Design
Ease of Design
Minimal skew
Minimal power
Rotary Traveling-Wave Oscillator?
H-Tree
Small regions
Design dependent
Design independent
Grid
Giant signals
Binary tree
?
?
Multi-VDD
Sloooowwwww systems (adiabatic systems, sine wave
clock) High VT systems
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New Clock Signal Distribution Technology Basics

• Closed switch starts wave around loop.
• Ideally, signal will propagate forever once
  started.

J. Wood, T. C. Edwards, Rotary Traveling-wave
Oscillator Arrays A New Clock Technology, IEEE
Journal of Solid-State Circuits, November 2001,
Vol. 36, No. 11
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Architecture

• Capacitance and inductance control speed of
  signal around loop.
• Loops linked by hard wired connections.
• Inverters placed to keep signal from degrading
  and to lock rotation direction.

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Performance

• Lperlength, Cperlength, and vp equations
  explained
• Heavily loaded, vp can be 0.03 x c 9 x 106 m/s
• fc ? vp / (2 x RingLength)
• ??? Performance limited by transit time, not
  inverter propagation time.
• ??? Rise/fall times controllable by setting
  cutoff frequency of transmission lines.
  Fcutoff 1/ ( 2??LlumpClump )

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More Performance metrics

• Changes in temperature and supply voltage.

• Changes in frequency due to supply voltage
  variation

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Power

• 84mA source whereas line current equals 200mA.
• Losses related to I2R rather than CV2f. Reducing
  R, increasing C, can increase I2R to unmanagable
  levels.

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Surges

• Simultaneous switching surges low because of the
  distributed switching times of the inverters.

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Tapoff Issues and Stub Loading

• Tapoff possible to extract clock. Generally can
  be looked at as capacitive stub on ring. To
  minimize signal distortion, ?p ltlt ?r, ?f
• Increasing of C indefinitely will reduce
  impedance and eventually Rloop lt 2Z0 and
  oscillation will stop.

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Logic

• Two-phase latched logic is thought to be most
  compatible. Two-phase reduces problem with
  current surges.
• Four-phase domino logic is possible if two loops
  of RTO available around logic.

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Layout questions

• Top level for clock nets
• Via parasitics insignificant due to size of
  inverters?
• Crossovers
• Two levels necessary to implement
• Electromigration
• Giant current In the future surges of gt 500 mA
  possible
• Inverters
• Located directly under lines
• Giant. Hard to switch? Use capacitors instead of
  transistor capacitance?

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Coupling Issues

• Strong magnetic field mitigated by running routed
  lines at 900 to loop lines on next lower metal
  layer. Works as electrostatic shield.
• ??? Substrate magnetic fields are to be expected.

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Interesting CAD

• A tool that targets a fixed operating frequency.
  Pads with capacitance to fix impedance
  discontinuities. Rotary Explorer.

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What Id like to do

• Better understand problems with design in paper.
• Come to conclusions on technology.
• Investigate compatible logic and applications for
  clock set-up.
• Check out CAD tools available.
• Solidify background on interconnect.