Fault-Tolerant design of RF front-end circuits

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Fault-Tolerant design of RF front-end circuits

• P.R. Mukund, Ph.D.
• Gleason Professor of Electrical Engineering
• Director, RF/Analog/Mixed-signal Lab (RAMLAB)
• Rochester Institute of Technology
• Rochester, NY 14623

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Funding
Industry Liaisons
This work was funded by the Semiconductor
Research Corporation
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Motivation

• SoC, SiP implementations
• High levels of integration
• Complex interaction between RF, analog, digital
  domains
• Heightened sensitivity to package parasitics,
  wide tolerances

• Mutual-coupling, electro-magnetic coupling, stray
  inductances
• Gap between models and silicon
• Several design iterations, higher costs and lower
  yield for RFICs

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Need for Fault-tolerance in RF circuits

• Complex behavioral, modeling and fabrication
  problems
• More faults and higher variations
• Poor, unpredictable Q-factors

• Testing is expensive (ATE)
• Very act of probing affects performance
• Access to RF core difficult
• Yield of RFICs 10-12 less than digital ASICs

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Background

• Self-test solutions with high overheads
• Computation, real-estate, DSP, power
• ATE testing very expensive (40 of chip cost)

Limitations

• Fault-tolerance in digital circuits
• Reconfigurability and redundancy
• Huge real-estate and power overheads for RF
• Fault-tolerance in analog circuits
• Feedback mechanisms
• Not practical for HF circuits
• Parametric fault-modeling for analog circuits

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Summary of Prior Work
Design Methodologies
Passive Characterization
Inductor Library
Novel Design Techniques
Inductor Libraries for RF Design
Inductor Modeling and Characterization
Vertically Integrated Designs (Si on Si)
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Prior BIST Architecture
TASKS Development of an accurate and
non-intrusive current monitor Fault modeling of
3D Stacked RF circuits Analyzing and quantifying
various factors leading to performance
degradation Development of current signatures -
Mapping circuit performance to supply
current. Integrating information into a BIST
architecture
Proposed BIST Architecture
Dr P.R.Mukund, RF / Analog / Mixed Signal Lab
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Feedback for RF circuits?
Why feedback will not work
Very little gain available for trade-off
Stability issues _at_ GHz Mutual coupling, Ground
loops, Metal trace parasitics
Alternative
Transformers, inductors, etc., have wide
tolerances
Feedback Re-design of circuit !
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This work.

• Alternative fault-tolerance methods for RF
  circuits
• Overcome limitations of traditional feedback
• Emphasis on low overhead, minimally intrusive,
  low-cost solutions
• Robust circuitry/algorithms for error-free
  operation
• Low-frequency/DC post-processing
• No DSP/off-chip processing, ultra-fast

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Methodology Locked loop concept
Specification based correction
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Locked Loop approach

• Four fold approach

• To sense a signal which is indicative of the
  performance metric of the circuit

Sense
Quantify
To process this signal appropriately into a form
which quantitatively describes the metric
Use this information to send a signal back to the
circuit where the metric can be re-corrected
towards the desired value
Self-corrective signal
A mechanism in the circuit which can adaptively
change its performance in real time based on the
above signal.
Tapped coil
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Minimally Intrusive Sensing
Small value
Current sensing HF transient current has
performance info
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Non-intrusive sensing

• Eliminate resistor for circuits with
  source-degenerative coils
• No measurable intrusion on LNA performance
• Over a narrow-frequency range, the source-coil
  can provide similar current-information as the
  resistor
• Gain and S22 sensed from source coil of mixer
  accounts for matching network

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Quantifying Specifications

• Two-tonal approach to quantify impedance
  matching
• Differential nature removes dependence on
  absolute values
• Highly robust and insensitive to process
  variations and soft faults in processing
  circuitry itself

• Gain sensed directly at mixer, using a third
  tone.
• Peak-peak value of this signal is a direct
  measure of gain

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Variable S11 The tapped coil
Dependence of gain, etc. on gm

• Digitally tapped gate inductor
• ASITIC Include all interconnects
• Switch size trade-off between on- resistance
  and capacitance

• Varies match frequency
• Tap the coil at several points in outer turn
• CMOS Switches
• Include switch and interconnect parasitics

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Variable Gain and S22

• S22 Bank of varactors at output node
• Gain Variable Transconductance array

Current-splitting variable transconductance
array eliminates S11 dependency CGS remains
constant on input-side
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Self-correction algorithm

• Minimal overheads
• No DSP, ADC or analog memory cell requirements,
  low power
• Ultra-fast, Low cost

VIDEAL
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Sensor chain
SF
Cascaded CS Stages
Peak Detector

• Source follower for isolation
• More stages for higher gain
• PD output stored on capacitors
• Op-amps for buffers, comparators
• Basic digital logic

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Results - Sensor chain
Tap no. sensor chain o/p for tone1(1.6GHZ) sensor chain o/p for tone2(2.2GHZ)
1 1098.54 mV 1391.57 mV
2 1112.85 mV 1375.63 mV
3 1128.67 mV 1365.23 mV
4 1150.61 mV 1356.95 mV
5 1166.88 mV 1355.01 mV
Output of Sensor Chain for all taps of Lg
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Simulation results - LNA
LG increase by 10
CGS reduction by 15
Weakest corner
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Experimental Results (1)

• Less than 10 of LNA area
• Re-used for other front-end circuits
• Turned on only during
• correction process

Spectral response
S11 -23 dB
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Experimental Results (2)
Tap no. Inductance Simulated S11 freq Digital word Measured S11 freq
1 7.4 nH 1.7 GHz 00 1.7375 GHz
2 9 nH 1.91 GHz 01 1.925 GHz
3 10 nH 2.0 GHz 10 2.03 GHz
4 11 nH 2.11 GHz 11 2.125 GHz
Measured transfer curve of the sensor chain

• Tapped Coil performance
• S11 magnitude stayed below -20 dB for all taps
• Match frequencies were 1.737 GHz, 1.925 GHz,
  2.03 GHz and 2.125 GHz.

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S22 and Gain correction (I)
Left S22 curves as varactor Bank is
varied Right Output spectrum of Sensor for
these S22 curves
Left Gain and S22 match varies as the load
inductor value varies Right Output of sensor
chain quantifying this variation
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S22 and Gain Correction (II)
Self-calibration of S22 Before (1.81 Ghz)
and After (1.89 GHz), for a 1.9 GHz LNA
Left Variation in the magnitude of Gain (due to
Q-factor variation of the load coil) Right
This Variation quantified by sensor
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Overheads

• Same circuitry re-used for all specifications
• Area overhead less than 10 of cascode LNA
• Can be re-used for other circuits of Front-end
• Losses in switches of the gate-coil
• NF degradation by 0.2 - 0.3 dB
• Power overheads
• Additional circuitry switched on only for
  duration of self-calibration negligible power
  overhead
• Current-splitting transconductance array uses
  additional current (5 - 10 overhead)

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Summary

• Fault-tolerant RF design has great relevance and
  applicability in an RFIC world of increasing
  complexity and massive integration
• Alternate, novel methodology for fault-tolerance
  in GHz domain
• Minimal overheads, no topological revision
• Ultra-fast (200 us) compared to existing test
  schemes (order of 100s of ms)
• Robust algorithms and post-processing techniques
• Demonstrated in silicon

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Publications (1)

• Journal Papers
• Tejasvi Das, Anand Gopalan, Clyde Washburn and
  P.R. Mukund, Self-calibration of RF front end
  circuitry, IEEE Transactions on Circuits and
  Systems, Dec 2005
• Tejasvi Das, Anand Gopalan, Clyde Washburn and
  P.R. Mukund, Towards Fault-tolerant RF
  front-ends, Journal of Electronic Testing
  (JETTA), Accepted for publication (Issue release
  Sep.06)
• Anand Gopalan, M. Margala and P.R. Mukund, A
  current based self-test methodology for RF
  front-end circuits, Microelectronics Journal,
  No.36, Aug 2005
• Anand Gopalan, Tejasvi Das, Clyde Washburn and
  P.R. Mukund, BiST for Multi-GHz CMOS RF
  Front-ends, IEEE Transactions on Circuits and
  Systems (Under review)
• Conference Papers
• Self-calibration of Gain and Output match in
  LNAs, IEEE ISCAS May 2006, Kos, Greece
• Towards Fault-Tolerant RF Front-Ends On-Chip
  Input Match Self-Correction of LNAs, The IEEE
  Mixed-signal Test Workshop, June 2005, Cannes,
  France.
• Dynamic Input match correction in RF Low Noise
  Amplifiers, 19th IEEE International Symposium on
  Defect and Fault Tolerance in VLSI Systems, Oct.
  2004, Cannes, France

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Publications (2)

• Conference papers (contd.)
• Use of Source Degeneration for Non-Intrusive
  BIST of RF Front-end Circuits, Proceedings of
  the International Symposium on Circuits and
  Systems, Kobe, Japan, May 2005
• An Ultra-fast, on-chip BiST for RF LNAs, 18th
  IEEE International Conference on VLSI Design,
  India, Jan. 2005.

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• Thank You