Thrust VI: Process Modeling, Simulation,

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Thrust VI Process Modeling, Simulation, and
Technology Assessment Co-leaders Krishna
Saraswat, Stanford Timothy Cale, RPI Other PIs
Duane Boning, MIT Antoinette Maniatty, RPI James
Plummer, Stanford Rafael Reif
Summary Develop, implement and use integrated
physically-based models to simulate the physical
structure, properties and viability of future
interconnect technologies, such as, 3D ICs.
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• Approaches
• Create a spectrum of physically based models
• atomic-level understanding of materials and
  structures
• ...
• macroscopic (across-chip) modeling of spatial
  variations
• Link process models to, higher level simulation
  tools
• Assess new technology and compare trade-offs in
  performance, manufacturability, and reliability

• Objectives
• Models to predict realistic structures and
  physical and electrical properties based on the
  fabrication process
• Assessment of new interconnect technologies using
  simulation and test structures

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Research Tasks

• Develop process models and test structures to
  predict physical and electrical properties.
• Atomic and mesoscopic level physically based
  models (RPI Stanford)
• Spatial geometry and parameter variations at long
  length scales (MIT)
• Develop methodology for integrated assessment of
  interconnect technologies
• Link process models to higher level simulation
  tools tradeoffs between performance and
  reliability (Stanford, MIT)
• Statistical interconnect design methodology
  -tradeoffs between variation and performance
  (MIT)
• Assess new interconnect technologies
• Analysis of alternative interconnects (e.g., air
  gaps, 3D ICs) (Stanford, MIT)
• Analysis of alternative robust clocking schemes
  (MIT)

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Back-End Simulation Methodology
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Air-Gap Interconnect Structures Performance and
Reliability

• Motivation
• Interconnect RC delay, crosstalk, noise, CV2f
  power all limit IC performance.
• Air-gaps reduce capacitance but may cause
  reliability process integration problems.

• Approach
• Characterize air-gap formation and performance
  using test structures.
• Use SPEEDIE to simulate depositions and identify
  deposition mechanisms.
• Use results to simulate interconnect performance,
  reliability, and manufacturability.

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Effects of deposition conditions on feature scale
spatial variation of properties of as deposited
thin films in interconnect structures

• Motivation
• Because of spatial variations in deposition
  parameters and topography, properties of
  interconnect structures such as grain structure,
  density, etc. vary with position.
• Spatial variations can cause performance and
  reliability problems.

Discrete model
Continuum model

• Approach
• Develop discrete models for the formation of
  microstructure.
• Develop granular continuum models to predict
  topography and composition.
• Develop models to predict spatial variation of
  physical and electrical properties as a function
  of deposition conditions and topography.
• Integrate with higher level models.

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Modeling of Physical Properties of Interconnects
during Thermal Cycling

• Motivation
• Microstructure and mechanical behavior can change
  during processing and thermal cycling.
• Void/hillock formation, grain growth, and
  dislocation glide/climb can occur.
• These changes can affect performance and
  reliability of interconnects.

Stress distribution in Al from cooling

• Approach
• Characterize mechanical behavior and
  microstructure in backend structures during
  processing
• Develop models and parameters to predict
  mechanical behavior given initial microstructure
• Integrate with other models and use for
  performance and reliability assessment.

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Modeling of Physical Phenomena in Polycrystalline
Structures

• Motivation
• Interconnect materials are non-homogeneous, with
  grains and grain boundaries (GB).
• In current interconnects, grain size approaches
  feature size
• Variability in GB properties leads to variability
  in interconnect performance
• Technologically relevant problems (e.g. hillocks,
  electromigration, resistivity) involve coupled
  diffusion, stress, boundary movement, thermal
  effects and electric field.

• Approach
• Build test structures to determine grain/grain
  boundary effects.
• Formulate the system of equations governing
  coupled stress/diffusion from thermodynamic
  considerations.
• Develop solution methods to capture effects of
  local variations in properties.
• Simulate real structures to assess performance
  and reliability of advanced interconnects.

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Statistical Modeling of Interconnect Variation

• Statistical interconnect design methodology is
  not well understood
• Inherently non- local e. g. critical paths
• Characterization and assessment of impact of
  random and systematic variation is needed

Effect on Delay of Global Paths
Spatial Variation Process Models
Layout Information
IBM 1 GHzProcessor
Mehrotra et al., IEDM 98

• Modeling
• Characterization via experimental test
  structures
• Coupling to technology - Assess new material,
  fabrication options
• Coupling to design
• Understand impact of variation
• Optimize interconnect approaches
• Asses alternative interconnect technologies

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3D ICs with Multiple Active Si Layers
Interconnect Delay

• Motivation
• Performance of ICs is limited due to R, L, C of
  interconnects
• Interconnect length and therefore R, L, C can be
  minimized by stacking active Si layers
• Number of horizontal interconnects can be
  minimized by using vertical interconnects
• TFT repeaters could be fabricated on top of a
  metal line

• Approach
• Compare the tradeoffs in performance,
  reliability and manufacturability of various
  approaches to 3D SOI through simulation and
  building test structures
• Compare the tradeoffs in performance by using
  TFT repeaters