FIR Design for SoC

1
FIR Design for SoC

• Status 4/22/2003
• Mahesh Dorai
• Narayanan Raghuraman

2
Design for FPGA

• DW Dual Port Ram Module targeted to FPGA
• Depth of 256 - 106
• Depth of 128 - 55
• FIR Module - 10
• Total for Input, Output Rams and FIR ? 120

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State Diagram for Ram Controller
RST
Start From Bus Arbiter
State 0 count
Count lt 128
State 1 Count check
Finish to Bus Arbiter
State 2 WR0 Finished1
4
SimplifiedBlock Diagram
TOP


Addr_read
Addr_write
Controller
FIR
Input Ram
Output Ram
Data_in
Data_out
Finish
Start/ Reset
Start
Clock-div
clock
5
Ram Controller Block Input Part
6
Ram Controller Block Output Part
7
Pre Layout SimsLoading input RAM
8
SimulationsStart sent to controller
9
Ram Controller Simulations
10
SimulationsFinish set High
11
Simulations Reading Output
12
Simulations Verifying with the FIR

13
Post-Layout Simulation Input RAM being loaded

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Work Done

• A Controller for the I/P , O/P Rams and FIR was
  designed
• I/P Ram was loaded with Input Data and Output was
  written to O/P RAM
• Simulations worked
• Layout was done using SE
• Synthesis for ASIC implementation was done

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• THANK YOU !!!