Statistical Gate Delay Calculation with Crosstalk Alignment Consideration

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Statistical Gate Delay Calculation with Crosstalk
Alignment Consideration
Andrew B. Kahng, Bao Liu, Xu Xu UC San
Diego http//vlsicad.ucsd.edu
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Outline

• SSTA Background
• Problem formulation
• Method theory and implementation
• Experiment
• Summary

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Background Variability

• Increased variability in nanometer VLSI designs
• Process
• OPC ? Lgate
• CMP ? thickness
• Doping ? Vth
• Environment
• Supply voltage ? transistor performance
• Temperature ? carrier mobility ? and Vth
• These (PVT) variations result in circuit
  performance variation

PVT Parameter Distributions
Gate/net DelayDistribution
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Background Timing Analysis

• Min/Max-based
• Inter-die variation
• Pessimistic
• Corner-based
• Intra-die variation
• Computational expensive
• Statistical
• pdf for delays
• Reports timing yield

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Background SSTA

• Represent signal arrival times as random
  variables
• Block-based
• Each timing node has an arrival time distribution
• Static worst case analysis
• Efficient for circuit optimization
• Path-based
• Each timing node for each path has an arrival
  time distribution
• Corner-based or Monte Carlo analysis
• Accurate for signoff analysis

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Background SSTA Correlations

• Delays and signal arrival times are random
  variables
• Correlations come from
• Spatial
• inter-chip, intra-chip, random variations
• Re-convergent fanout
• Multiple-input switching
• Cross-coupling

g1
corr(g1, g2)
g2
corr(g1, g3) corr(g2, g3)
g3
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Multiple-Input Switching

• Simultaneous signal switching at multiple inputs
  of a gate leads to up to 20(26) gate delay mean
  (standard deviation) mismatch Agarwal-Dartu-Blaau
  w-DAC04

Probability
Gate delay
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Crosstalk Aggressor Alignment

• We consider an equally significant source of
  uncertainty in SSTA, which is crosstalk aggressor
  alignment induced gate delay variation

MIS
CAA
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Problem Formulation

• Given
• Coupled interconnect system
• Gate input signal arrival time distributions
• Find
• Gate output signal arrival time distributions
• We present signal arrival times in polynomial
  functions of normal distribution random variables
• E.g., for first order approximation of two input
  signal arrival times, their skew (crosstalk
  alignment) is given in normal distribution random
  variables with correlation taken into account

xi fi(r1, r2, ) ri N(mi, 3si)
x1 N(m1, 3s1) x2 N(m2, 3s2) xx2-x1
N( mm2-m1, 3s3(s12s22corr)1/2)
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Outline

• SSTA Background
• Problem formulation
• Method theory and implementation
• Experiment
• Summary

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Driver Gate Delay as a Function of Crosstalk
Alignment
16X inverters driving 1000um global
interconnects in 70nm technology
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Driver Gate Delay as a Function of Crosstalk
Alignment

• More complex than the timing window concept
• Can be computed by simulation or delay
  calculation
• Approximated in a piece-wise quadratic function

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Closed-Form Driver Gate Delay Distribution

• For a normal distribution crosstalk alignment x

• Transform probabilities via inverse functions

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Closed-Form Driver Gate Output Signal Arrival
Time Distribution

• For a normal distribution crosstalk alignment x

• Consider correlation via conditional probabilities

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Statistical Gate Delay Calculation for Coupled
Interconnect Load

• Input Coupled interconnects
• gate input signal arrival time distributions
  
• process variations
• Output Gate output signal arrival time
  distributions
• Driver Gate delay calculation for sampled
  crosstalk alignments
• Approximate driver gate delay in a piece-wise
  quadratic function of crosstalk alignment
• Compute output signal arrival time distribution
  by closed-form formulas
• Combine with other process variations

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Extension to Multiple Aggressors

• In general, superposition does not apply for
  multiple aggressors because of driver output
  resistance variation
• We need to
• Extract empirical functional relationships
  between driver gate delay and aggressors
• Compute gate output signal arrival time
  distributions
• Superposition applies for long interconnects with
  large drivers of small output resistance

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Extension to Multiple Variations

• Correlated variation sources
• Reduce the number of variations, via PCA
• Extract empirical functional relationships
  between gate delay and variations
• Compute gate output signal arrival time
  distributions
• Independent variation sources
• Applying Superposition for improved efficiency

?total ?i ?i ?2total ?is2i
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Implementation

• STA-SI goes through an iteration of timing window
  refinement for reduced pessimism of worst case
  analysis
• SSTA-SI goes through an iteration of signal
  arrival time pdf refinement with reduced
  deviations

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Runtime Analysis

• Driver gate delay calculation for N sampled
  crosstalk alignment takes O(N) time, where N
  min(t3-t0, 6 s of crosstalk alignment) /
  time_step
• Fitting takes O(N) time
• Computing output signal arrival time distribution
  takes constant time, e.g., updating in an
  iterative SSTA

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Outline

• SSTA Background
• Problem formulation
• Method theory and implementation
• Experiment
• Summary

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Experiment Setting

• 16X inverter drivers
• Coupled global interconnects in 70nm Berkeley
  Predictive Technology Model
• Extracted coupled interconnects of 451 resistors
  and 1637 ground and coupling capacitors in 130nm
  industry designs

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Driver Gate Delay Distribution

• For a pair of 1000um coupled global
  interconnects in 70nm BPTM technology, with 10,
  20, 50 and 100ps input signal transition time,
  and crosstalk alignment in a normal distribution
  N(0, 10ps)

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Driver Gate Delay Standard Deviation due to
Varied Gate Length

• For a pair of 1000um coupled global
  interconnects in 70nm BPTM technology, with 10,
  20, 50 and 100ps input signal transition time,
  and wire width variation in a normal distribution
  N(0, 15)

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Driver Gate Delay with Gate Length and Crosstalk
Alignment Variations

• No variation
• Gate length variation
• Crosstalk alignment variation
• Superposition results of both variations
• SPICE results of grounding coupling capacitors
  and both variations
• Our results of both variations

16X inverter drivers of coupled 70mm BPTM global
interconnects
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Driver Gate Delay with Gate Length and Crosstalk
Alignment Variations

• Superposition of gate length and crosstalk
  alignment variations matches within 2.20 of
  SPICE Monte Carlo results
• Assuming no crosstalk alignment (e.g., grounding
  all coupling capacitors) results in
  159.4(147.4) mismatch in mean (standard
  deviation) of driver gate delay variation

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Driver Gate Output Signal Arrival Time
Distribution

• For a pair of 1000mm coupled global
  interconnects in 70nm BPTM technology, with 10,
  20, 50 and 100ps input signal transition time,
  and crosstalk alignment in a normal distribution
  N(0, 10ps)

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Driver Gate Output Signal Arrival Time
Distribution
Test case 1 1000mm interconnects of 70nm
BPTM technology
Test case 2 coupled interconnects in a
130nm industry design
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Outline

• SSTA Background
• Problem formulation
• Method theory and implementation
• Experiment
• Summary

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Summary

• SSTA must consider SI effects!
• We take crosstalk aggressor alignment into
  account in statistical gate delay calculation
• We approximate driver gate delay in a piecewise
  quadratic function of crosstalk aggressor
  alignment
• We derive closed-form formulas for driver gate
  delay and output signal arrival time distribution
  for given input signal arrival times in
  polynomial functions of normal distributions
• Our experiments show that neglecting crosstalk
  alignment effect could lead to up to 159.4
  (147.4) mismatch of driver gate delay means
  (standard deviations), while our method gives
  output signal arrival time means (standard
  deviations) within 2.57 (3. 86) of SPICE
  results

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Thank you !