Securing Embedded Systems

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Securing Embedded Systems

• tepán Kopriva
• koprivas_at_msoe.edu
• SE-4920

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Introduction
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Growing field of embedded systems

• Fastest growing field in computer business
• PDAs, Smart Cards, Digital music players
• Heart monitoring device
• Sensor monitoring water quality
• Futuristic technologies on the horizon
• Embedded network sensors
• Wearable computers

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Security of embedded systems

• Systems
• Resource constrained in capacities
• Easily accessible at physical layer
• Security
• Cant be solved at a single abstraction layer
• Biometric authentication device

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Embedded design challenges
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Characteristics of embedded system

• Processor based devices
• Portable
• Communicate via wireless channels
• Its tempting to port workstation based security
  on embedded systems
• Resource limitation
• Physical accessibility

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Resource limitation I

• Smart-Dust node
• 4 MHz 8-bit CPU
• 8000 bytes of instruction memory
• 512 bytes of RAM
• 512 bytes of EEPROM
• Battery-powered

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Resource limitation II

• Public key cryptography (RSA)
• Infeasible because of memory
• Infeasible because of processor horsepower
• Infeasible because of battery exhaustion

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Physical accessibility

• Devices are easily accessible at the physical
  layer
• Physical tampering
• Side-channel analysis
• Differential Power Analysis
• Monitoring smart cards power line to extract the
  cards cryptographic key

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Physical accessibility II

• Privacy concerns
• Data only in one location compared to servers
• If the device is stolen, it needs extra security
  measures built-in

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Embedded security pyramid
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Embedded security pyramid
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Protocol level

• Design of the protocol
• Is responsible for
• Confidentiality
• Identification
• Data integrity
• Data origin authentication

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Algorithm level

• Design of cryptography primitives
• Block cyphers
• Hash functions
• Application specific algorithms
• Algorithms used at the protocol level

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Architecture level

• Hardware software partitioning
• Embedded systems to prevent hacks

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Microarchitecture level

• Hardware design of modules required and specified
  at the architecture level
• Processors
• Coprocessors

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Circuit level

• Implementing technics to thwart physicall layer
  attacks
• Transistor level
• Package level

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Security types

• Single level
• Problem and the remedy are at the same level of
  abstraction
• Translevel
• The problem at one level can be solved only with
  remedy at another level (lower).
• Every level must be secure

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Building the pyramid
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Wirelles biometric authentication device (WBAD)

• CMOS fingerprint sensor
• 32-bit RISC controller
• Embedded memory
• Biometric hardware
• Security hardware
• Infrared wireless transmitter

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WBAD Server based scheme I
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WBAD Server based scheme II

• User enters claimed identity
• Magnetic card
• Smart card
• Server validates the identity
• User impresses fingerprint on the servers senzor
• Server compares the fingerprint with a previously
  stored template

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WBAD Server based scheme III

• Security flaws
• Residual fingerprint image stays on the public
  sensor
• Storing the fingerprint on the server can be
  considered a privacy violation

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WBAD Device based scheme I
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WBAD Device based scheme II

• User interacts just with the device
• The device authenticates both itself and the user
  with a fixed server
• All biometric-processing algorithms are performed
  on the device
• Server stores a keyed hash of biometric template

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Protocol level Verification protocol
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Protocol level II Single level security flaw

• Server masquerade attack
• Device never authenticates RANDRANDT
• False server could send these values undetected
• Solution
• Additional hash from server H(SK,RANDRANDTID)
  where MAC is a message authentication code

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Protocol level II Translevel security flaw

• Bypass attack
• Adversary inserts malicious software to bypass
  the biometrics function
• Directly after receiving the rand numbers, the
  hacked program loads the key K telling that the
  match has been made
• Server assumes that the device works properly
• Cant be solved on protocol level

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Algorithm level I

• Cryptographic algorithm
• Advanced Encryption Standard
• 128 cipher (128-bit key, 128-bit data)
• C E(K,P)
• Keyed hash function
• Cipher-block chaining MAC mode
• Hashing a variable-length data stream D to a
  fixed 128-byte hashH(K,D)

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Algorithm level II

• Signal-processing algorithms
• Feature-extraction algorithm
• Extracts the minutiae from the raw image
• Matching algorithm
• Performs a matching operation between the
  minutiae and a stored template

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Architecture level I

• Protocol and algorithm are mapped onto an
  embedded architecture platform
• Security partitioning
• Secure modules
• Insecure modules
• Clearly distinguish between secure and insecure
  parts

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Architecture level II
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Architecture level III

• Single chip solution
• Two modules connected by a secure insecure bus
• Easy programmability
• Waste of area and power

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Architecture level IV
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Architecture level V

• Dual chip solution
• Each module designed independently
• Secure-to-insecure bus accessible on the board
• Additional power and additional protocols
  (handshaking) needed

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WBAD architecture

• Single chip insecure microprocessor and secure
  coprocessor
• Microprocessor - Leon
• 32 bit RISC
• Embedded Sparc V8 open source core
• Coprocessor
• Custom designed

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Architecture level VI

• Coupling between modules
• Loosely coupled (memory mapped)
• Performance advantages
• Design time disadvantages
• Tightly coupled (register mapped)
• Our design
• Memory mapped coprocessor
• 3 buses between secure and insecure part
• 16 bit INS, 32 bit D_IN, 32 bit D_OUT

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Architecture level VII
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Architecture level VIII

• Mapping phase
• Map protocol functions on secure/insecure modes
• Secure functions on secure coproccesor, which is
  accessible to processor through instruction set
  only

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Architecture level IX

• Secure instruction set
• To protect secure functions from software bypass
• Processor accesses coprocessor via two
  instructions
• DO_MATCHING
• DO_CRYPTO

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Architecture level X

• DO_MATCHING
• Loads the stored template
• Matches it to the candidate minutiae
• Sets match flag internal to coprocessor
• Coprocessor sends READY_FOR_CRYPTO signal
• Indicates that the matching is completed
• Sends this signal after constant number of cycles

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Architecture level XI

• DO_CRYPTO
• Coprocessor
• Loads the internal flag
• Performs cryptographic steps to produce the token
• Token is returned to processor and send to the
  server
• Insecure processor doesnt have any way to set
  the match flag high other than through biometric
  processing

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Architecture level XII

• Information sent on the bus
• READY_FOR_CRYPTO signal
• Token
• Insecure processor cant decrypt it because it
  doesnt know the key K

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Microarchitecture level I

• Hardware implamantation
• Insecure part Leon processor
• Secure part
• Custom design of coprocessor
• Hardware coprocessor reduces energy needed for
  encryption
• AES - 10Gbits/joule compared to 10Kbits in Java

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Microarchitecture level II

• Secure module
• Top-level controller
• Cryptographic engine
• Matching engine
• Private buses
• Secure buses internal to coprocessor
• Public buses
• Coprocessors interface to the outside world

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Microarchitecture level III

• It is necessary to simulate secure and insecure
  modules together
• Boundary between hardware and software is often
  week part of the system
• Top level controller constraints
• Allowed combination of instructions
• Security vs. flexibility

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Circuit level I DPA

• CMOS the standard building block
• The only transaction that causes dynamic power
  dissipation from the power supply is 0 gt 1
  output transaction
• 1 gt 0 transaction output capacitance
  discharges to ground
• During 0 gt 0 and 1 gt 1 circuits use no dynamic
  power

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Circuit level II combating DPA

• The ciurcuit needs to have the same dynamic power
  dissipation regardless the transaction Sense
  amplifier based logic (SABL)
• Charging the same capacitance at every event

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Circuit level III
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Circuit level IV

• SABL disadvantages
• Power It doubles average power consumption
• Area It roughly doubles the area