Agenda

1
Agenda

• Design Flow
• Circuit Design
• Process Design
• What is semi custom design?
• Example
• Device physics

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Circuit Design Flow

• Receive/develop logic, power, timing, area
  specification (gain, bandwidth )
• Get logic working in verilog or vhdl
• Size transistors by hand
• Verify in schematic spice adjust W/L
  appropriately
• Layout and re-verify all specifications
• Fabricate
• Test

3
Process Design Flow

• Determine rough thickness of oxides and junction
  depth pick process and supply Voltages and VT
• Use hand calculations to pick doping levels
• verify that the oxide will be thick enough for
  the voltage range
• Xj does not violate Break down rules
• Design Process with athena cad tool
• Verify the process in silicon
• Develop tech file so a design can use your
  process
• spice deck, DRC LVS checks, VT ,RS
• Keep process under control

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Sample Layout Design Rules

• Make sure that we have a high yield on our
  fabrication process.
• How many transistors meet specification out of
  how many we made.
• This need to be as close to one as possible.
• If there is no duplication of functionality one
  bad transistor can make a 10 million transistor
  CPU fail!
• Low yields force you to test more of your
  circuits.
• Testing represents a significant amount of the
  fabrication costs

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Alignment Errors
We need to have a minimum overlap of the metal to
contact to take into account the inherent
errors in alignment.

• A- No Errors
• B- Worst Case x misalignment
• C- Worst Case y misalignment
• D- Worst case x and y

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Minimum Feature Size

• The smallest
• gate length we can manufacture reliably
• Depends on PL and Etch
• smallest diffusion region
• Depends on PL and Etch
• minimum separation of diffused regions
• Depends on how far junctions diffuse during
  processing
• minimum separation of metal lines
• Depends on PL, Etch and electrical
  characteristics
• minimum contact width
• Depends on Etch, PL and contact resistance

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Design Rules for Our NMOS Process

• For high yields we need to have a process that
  can withstand large process variations
• ½ of our smallest feature size is equal to l.
• l is equal to 8 mm

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Design Rules for Our NMOS Process
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Transistor
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Resistor
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Alignment Rules

• Source/Drain Resistors- First Mask
• Thin oxide mask- Align to level 1
• Contact window mask- Align to level 1
• Metal mask- Align to level 2

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Review

• Oxide Thickness
• For Field oxide solve for minimum thickness to
  achieve a large VT
• Choose a growth method and temperature and solve
  for time
• For Gate Oxide solve for an oxide thickness to
  achieve a VT of around a volt
• Choose a growth method (wet or dry) and growth
  temp and solve for time

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Review

• Diffusion
• Pick a sheet resistance
• Pick a junction depth, and temp, solve for time
• (for now assume that the sheet resistivity will
  be correct)

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Review

• Process
• Field oxide
• S/D Diffusion
• Gate oxide
• Contact
• Metalization

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Electrical Calculations
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Electrical Calculations
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Semi Custom IC design

• The most expensive and time consuming layers are
  pre-processed
• S/D diffusion, Gate oxide, contact, and
  metalization
• Circuits are made by wiring together the pre laid
  out transistors.
• One mask is made and PL done on wafers.
• Since the wafers are predone the turn around time
  is very short.
• Since the transistors are pre laid out design
  time is reduced!

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Resistor Pass-through
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MOSFET
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Blank Logic Cell Schematic
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Blank Logic Cell Layout
Metal1 and S/D diffusion are connected by the
contact layer, otherwise they pass over each
other. Metal1 crossing a Metal1is a short as is a
S/D cross.
Green S/D Diffusion Red Gate Oxide Orange
Contact Blue Metal1
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INV Schematic
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INV Layout
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NAND3 Schematic
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NAND3 Layout
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NOR3 Schematic
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NOR3 Layout
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Cells Snap Together
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AND3 Layout
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Can you do a two input mux?
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Modeling the MOSFET
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VT0
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VT short channel
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VT

• VT changes with VSB

This will cause trouble later.
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Mobility

• Mobility changes with electric field
• The constant KNP, is never constant
• We use an average

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l

• This is due to the channel length narrowing.
• The reversed biased diodes depletion region gets
  bigger with VDS, and thus the length of the
  channel gets smaller, and thus the ID goes up.

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What does the circuit design engineer control?

• How big W and L are.
• How the wires are connected.
• This does not sound like much is it is a lot.

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What does the process design engineer control?

• Tox
• Na
• Junction Depth
• Qi (kind of)

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What doe we have to do?

• We need to finalize the process so we have
  reasonable VT, l, g and KNP values.
• We really need a positive threshold VT.
• Gate oxide experiments.
• Try and find out l, g and KNP from the current
  process so we can finalize mask design. (testing)
• Finalize mask design.

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What doe we have to do?

• Verify design environment (drc, lvs etc.)
• Verify logic cell
• Develop analog leaf cell
• Think about cool things we can put on the mask.
• Develop Cox, Rs test structures.

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What do we have to do?

• Learn fabrication equipment
• Learn test equipment
• Develop automated l, g and KNP extraction
  routines.
• Develop Athena run deck to match process
• Write Traveler linked to run deck