Direct Memory Access

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Direct Memory Access

• Eileen McCormack

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• Learning Objectives
• Able to Define Direct Memory Access (DMA)
• Generally describe the DMA transfer process and
  the Key hardware involved
• Understand the benefits of DMA Use
• Presentation Outline
• Definition of DMA and Benefit of Use
• Brief Review of CPU Driven Memory Access
• Overview of DMA Process
• DMA Controller
• Summary
• Bibliography

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Direct Memory Access (DMA)

• Direct Memory Access (DMA) allows for the reading
  of and writing to of Memory without transmitting
  data/addresses through the CPU
• DMA provides increased efficiencies by
• Allowing higher transmission rates to Memory than
  those provided by CPU
• Freeing the CPU for more productive use of cycles

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Overview of Direct Memory Access

• Each I/O device can be DMA capable or the I/O
  devices can be connected to a DMA controller
• The DMA has an address. Two or more I/O devices
  can share the same address.
• The DMA controller contains
• Buffers (data, address)
• Registers(address, count, control)
• Control Logic

DMA Controller
I/O Device DMA Capable
I/o Device DMA Capable
I/O Device DMA Capable
I/O Device
I/O Device
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CPU Driven Memory Access

• CPU issues R/W request, sends memory address,
  sends data if write (semisynchronous
  transmission) along the bus.
• Simple hierarchy, Memory searched starting with
  Cache, then Main Memory, etc. Blocks moved from
  rightmost Mem to Cache, Word to CPU
• System to update Main Memory with Cache updates
  (write through, write back)
• Complete signal issued Memory to CPU, data (word)
  sent to MD if read request

CPU
Memory Hierarchy
Address Bus
MA
Registers
Register
Main Memory
Data Bus
MD
Cache
Mem
R/W
Request
Complete
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Overview of DMA Process

• DMA signals a bus request to the CPU to Become
  Bus Master

MemControl
CPU
Memory
Address
Data
I/O
I/O Control
Memory Mapped I/O
CPU is default Bus Master, but DMA takes
precedence DMA asserts request, wait for bus
grant, asysnchronous Prioritization Systems for
Bus Arbitration -Daisy Chain ( Devices
pre-prioritized ) -Centralized (Individual
devices make request to central
unit) -Distributed (Individual devices make
prioritization)
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DMA Initialization

• The CPU initializes the DMA providing it with
  information needed to effect transfer including
  memory address, count, transfer type
• When BG 0, CPU can R/W to DMA. When BG is 1 ,
  DMA is Bus Master and CPU can no longer
  communicate unless the DMA passes the baton

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Overview of DMA Process

• Bus Grant sent by CPU , DMA Transfer Proceeds
• DMA controller effects control signals to
  handshake with I/O device.
• Alternative transfer techniques can take place
• cycle stealing or word by word transfer where
  DMA steals a cycle from the CPU to R/W. Bus
  masterhip must be relinquished and reqained if
  you just steal a cycle.
• burst transfer allows for a block sequence
  with a number of words transferred in a
  continuous burst with bus mastership retained
  until completion
• Transfer and Control relationship The I/O
  effects transfer on data bus under the auspices
  of the DMA controller. During Transfer DMA
  increments address, decrements count, and tests
  to see if count 0 i.e. transfer is complete.
  If not then checks to see if peripheral is making
  DMA request to send next word/more data. If so
  continue loop of word by word transfer until
  entire block (count) is transferred. When count
  0 and no peripheral request loop terminates.
• Release bus when transfer complete
• Uses interrupts to signal CPU
• CPU default bus master

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DMA Controller

• Central controllers with I/O connected called
  channel
• Each channel needs its own address and count
  registers

DMA Controller
I/O Device
I/O Device
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DMA Channel

• Selector Channel - one device at a time yet has
  many devices connected. Has only one set of
  registers.
• Multiplexer Channel - can control several block
  transfers at once. Has registers for each I/O
  device connected

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Summary

• Direct Memory Access provides an efficient way to
  transfer blocks of data to memory by
  circumventing the CPU, prioritizing request
  amongst I/O devices, and interweaving bus demand
  for memory to minimize idle time.
• DMA makes use of a controller with buffers,
  registers, control logic to control and effect
  the transfer of data between memory and I/O
  devices
• DMA trades but never shares mastership with the
  CPU for the memory bus

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Bibliography

• Texts
• Computer Systems Design and Architecture,
  Heuring, and Jordan, Pearson Prentice Hall 2004
• An Introduction to Computer Science, Schneider
  and Gersting, thomson.com, 2nd Edition 1999
• Computer System Architecture, Mano, Prentice
  Hall, 3rd Edition, 1993
• Computer Architecture, Baron, Addison Wesley
  1992
• Advanced PC Architecture, Buchanan Wilson,
  Addison Wesley 2001
• Internet Sites
• Direct Memory Access (DMA) Modes and Bus
  Mastering DMA and Ultra DMA (UDMA) Modes
  http///www.pcguide.com/ref/hdd/if/ide/modesDMA-c.
  html
• Direct Memory Access, en.wikipedia.org/wiki/Dire
  ct_memory_access
• Open Courseware
• Stanford University, C.Kozyrakis,
  http/eeclass.stanford.edu/ee282, lecture 9-I/O
• Rice University,C.J.Ganier, http//cnx.rice.edu/co
  ntent/m11867/latest/
• MIT,http/ocw.mit.edu/OcwWeb/Electrical-Engineerin
  g-and Computer-Science/6-828Fall2003
• Princeton University, Kai Li, http/www.cs.princet
  on.edu/courses/cos318/ and http/www.princeton.edu/
  wolf/EE464/overheads/ch4-2.ppt