ENSC 150

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ENSC 150
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• Synchronous Circuits

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Agenda

• more about flip-flops sections 4.1 to 4.3
• grouping flip-flops - registers sections 5.1
  and 5.2
• parallel and serial data format
• shift registers section 5.3

We will come back to sections 4.4 to 4.7 later.
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D-Type Flip-Flop
Note The signals set, clr perform their
function on Q when they attain a value of 1. We
say that the signals are active high because
they activate their function when their level is
a high.
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Active Low Signals
Note The signals set, clr perform their
function on Q when they attain a value of 0. We
say that the signals are active low because
they activate their function when their level is
a low.
Sometimes the signal will also be named clr or
set to indicate that the signal is active low,
however the correct indicator of the active level
is bubble at the terminal.
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Negative-Edge Clocks
The bubble on the clock terminal tells us that
the synchronizing function of the clock signal
happens at the instance when the clock falls from
a 1 to a 0.
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Example
Note the transitions of Q always line-up with
the rising edge of CLK except for the case when
either SET or CLR are active.
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D-Type Latch
Note Q is able to follow D while the clock is
high. When the clock is low, the last value of Q
is latched into the cell.
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J-K Flip-Flop
Exercise Try to predict Q from the inputs.
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Synchronizing Words
Sometimes a group of binary signal lines
represent a more complicated abstract object such
as a number or code. It is often useful to
synchronize these lines.
Each bit is passed through its own d-type
flip-flop. All the flip-flops share a common
clock signal. The collection of flip-flops is
called a register.
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Example
synchronizing the flow of data as two operands
flow through an adder.
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Note The output register held the result from
the previous addition valid while the new
calculation was rippling through the adder
circuit.
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Parallel Data
Consider a circuit which processes a sequence of
4-bit numbers. We could send the numbers into the
circuit one at a time using 4 signal lines.
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Serial Data
Sometimes we do not have enough signal lines to
carry parallel data. eg. Phone lines. Instead we
place the individual bits onto 1 signal line, one
at a time.
Sometimes the data is inherently serial. eg bits
that control the intensity of the electron gun in
a display unit.
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Parallel to Serial Conversion
How can we build a circuit which converts 4-bit
parallel data to serial data?
1) We begin by loading the parallel data into a
4-bit register.
2) Then we load the register with its own value
but with the bits misaligned.
3) Repeat step 2) two more times.
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How is Fig 5-6 page 259 different from this
circuit? Draw the timing waveform for SEL and CLK
to convert a stream of 4-bit parallel numbers to
a serial data stream.