Lecture 6: Edgetriggered FlipFlop, State Table, State Diagram

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Lecture 6 Edge-triggered Flip-Flop,State
Table, State Diagram

• Soon Tee Teoh
• CS 147

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Edge-triggered Flip-Flop

• Contrast to Pulse-triggered SR Flip-Flop
• Pulse-triggered Read input while clock is 1,
  change output when the clock goes to 0. What
  happens during the entire HIGH part of clock can
  affect eventual output.
• Edge-triggered Read input only on edge of clock
  cycle (positive or negative)
• Example below Positive Edge-Triggered D
  Flip-Flop (Fig 6-13, pg. 253)
• On the positive edge (while the clock is going
  from 0 to 1), the input D is read, and almost
  immediately propagated to the output Q. Only the
  value of D at the positive edge matters.

D
Q
S C R
D C
Q
Clock
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Symbol

• Symbol of edge-triggered D flip-flop

D C
D C
Negative-edge triggered
Positive-edge triggered
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Flip-Flop Timing

• Set-up time ts
• Input needs to be stable before trigger
• Hold time th
• Input needs to be stable after trigger
• Propagation delay tp
• Some delay from trigger to output change
• Example Negative edge triggered flip-flip

Clock
ts
th
tp
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Sequential Circuit Description

• Input Equations
• State Table
• State Diagram
• Well use the following example

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Sequential Circuit Description
X
A
D C
A
B
D C
B
Clock
Y
From Figure 6-17, page 259
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Sequential Circuit Description
Next state Present state
X
A
D C
input
A
B
D C
B
Clock
Y
At the clock trigger, the next state will be read
and transferred to the present state
output
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Input Equations
Anext ApresentX BpresentX
Next state in terms of input and present state
Bnext ApresentX
Output in terms of input and present state
Y (Apresent Bpresent)X
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State Table
Present State Input Next
State Output A B
X A B
Y 0 0 0
0 0 0 0 0
1 0 1
0 0 1 0
0 0 1 0 1
1 1 1
0 1 0 0
0 0 1 1
0 1 1
0 0 1 1 0
0 0 1 1
1 1 1
0 0
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State Diagram
1/0
0/0
00
01
0/1
0/1
1/0
0/1
11
10
1/0
1/0
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Mealy and Moore Models

• Preceding Example Output depends on present
  state and input. This is called the Mealy Model
• Another kind of circuit Output only depends on
  present state. This is called the Moore Model

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Example of Moore Model
X Y
A
Z
D C
Anext Apresent XY Z Apresent
Clock
X Y Apresent Anext 0 0 0
0 0 0 1 1 0 1 0
0 0 1 1 1 1 0 0
0 1 0 1 1 1 1 0
1 1 1 1 1
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00,01,10
0/0
1/1
00,01,10,11
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Moore Model
Some Combinational Circuit
Inputs
Some Combinational Circuit
Outputs
Flip-flops
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Mealy Model
Some Combinational Circuit
Inputs
Some Combinational Circuit
Outputs
Flip-flops
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Mealy and Moore ModelState Diagrams
1/0
0/0
00
01
Moore
input
0/1
0/1
1/0
0/1
input
output
11
10
11
1/0
00,01,10
1/0
0/0
1/1
state
Mealy
state output
00,01,10,11
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How to Design a Sequential Circuit

• 1. Specification
• 2. Formulation Draw a state diagram
• 3. Assign state number for each state
• 4. Draw state table
• 5. Derive input equations
• 5. One D flip-flop for each state bit

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Example

• Design a sequential circuit to recognize the
  input sequence 1101.
• That is, output 1 if the sequence 1101 has been
  read, output 0 otherwise.

1/0
0/0
0/0
1/0
1/0
A
B
C
D
0/0
1/1
0/0
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Assign States

• 4 states, so we need 2 bits

1/0
0/0
0/0
1/0
1/0
00
01
10
11
0/0
1/1
0/0
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Draw State Table
Present State Input Next
State Output A B
X A B
Y 0 0 0
0 0 0 0 0
1 0 1
0 0 1 0
0 0 0 0 1
1 1 0
0 1 0 0
1 1 0 1
0 1 1
0 0 1 1 0
0 0 0 1
1 1 0
1 1
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Derive Input Equations
Anext ABX AB Bnext ABX ABX
ABX Y ABX
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Draw Circuit
X
A
D C
A
B
D C
Exercise Fill in the input to Flip-Flop B
B
Clock
Y