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SoftwareOnly Bus Encoding Techniques for an Embedded System

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Software-Only Bus Encoding Techniques for an Embedded System ... IO bus (Compact Flash PCMCIA) PCMCIA/CF interface. Voltage : 3.3 V ... – PowerPoint PPT presentation

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Title: SoftwareOnly Bus Encoding Techniques for an Embedded System


1
Software-Only Bus Encoding Techniques for an
Embedded System
  • Wei-Chung Cheng, Jian-Lin Liang, Massoud Pedram
  • ASC-DAC 2002

2
Introduction
  • Goal
  • The application of system-level or software-level
    techniques to reduce power consumption on the
    data bus and IO bus.
  • NO! Hardware modification using off-the shelf
    product

3
Target System(SA1110 evaluation board)
4
Data Bus (Memory LCD controller)
  • LCD background
  • 320 240 pixel, 24 bit color depth, 60Hz
  • 3202402460 111 M bit / sec (bps)
  • Using 256 color palette a simple
    one-dimensional index table, which in turn
    represents a 24 bit color
  • 320240860 37 M bit / sec
  • Decoding performed by the LCD controller

5
Problem formulation
  • Power model on D_bus switching activity
    (Hamming distance) ? minimizing the switching
    activity by changing the palette table

6
Palette Encoding Algorithm (SA)
  • State transition graph G
  • By a simulated annealing algorithm, we can find
    the solution.
  • overhead SA algorithm is run only once per
    image to create the color-mapped image ? ignore

7
Palette Encoding Algorithm (PS)
  • In black and white image, the color brightness is
    likely to change continuously
  • ? Sort the palette by their brightness and use
    gray code. (palette sorting algorithm)

8
Experimental results (Palladia)
  • GUI and image

sparse
continuous
GUI
Image (PS-based Heuristic)
9
IO bus (Compact Flash PCMCIA)
  • PCMCIA/CF interface
  • Voltage 3.3 V
  • Capacitance high (PCMCIA adapter card is
    physically long)
  • Frequency high (the speed of solid-state
    memory)
  • ? The power dissipation on the bus can be quite
    high

10
PCMCIA bus encoding
  • Bus Invert algorithm (stan 95)
  • Processing step
  • File is divided into blocks
  • Each block is analyzed to derive the best pattern
  • The 16bit pattern xor 16 bit words in block
  • The results are written back to the file
  • Difference
  • No needing extra hardware
  • The calculation of the inversion pattern at the
    compile time
  • Redundant information is carried in the file
    header
  • The inversion pattern is changed for each block
    of data to adapt to the specific characteristics
    of the block

11
IPS problem formulation
  • Goal reduce the power consumption of a mobile
    system in which the applications are predefined.
  • The optimization problem can be solved off-line
    without about power dissipation overhead.
  • (ex branch-and-bound algorithm)

12
Experimental results
Better results
Marginal improvement is not impressive
?
Variable block size ? Select 4K
10-26 reduction , by very simple
modification of OS.
Block size 4K
13
Conclusions
  • Data bus ( LCD memory )
  • Reassign the palette and rewrote entries in the
    pixel buffer according to their correlation to
    the image
  • 29 reduction in text mode (GUI)
  • 17 reduction in graphic mode (image)
  • IO bus ( CF - PCMCIA )
  • 26 reduction by a very simple modification of
    the OS kernel (fixed version)
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