Embedded test tutorial

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Logic BIST
Logic BIST
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Requirements for BIST-able designs

• Scanability
• connectivity and tracing
• data propagation
• clocking
• No bus conflicts
• No X state propagation to observable outputs
• Random pattern testability

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Sources of X states

• Violation on a TIE-X gate
• Violation on a transparent latch
• ROMs or RAMs
• Violation on a bus
• Non-scan cell

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Effect of X propagation to MISR
Every unknown value can double the number of
correct signatures
Test response
Signature
0011010010111100101
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Control of three-state drivers

• Avoid using three state drivers
• Exactly one driver should be active at any time
  in normal and test mode

decoder
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Preferred mux-based implementation
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Feedback loops

• Unknown oscillatory state
• X bounding by blocking the output of the loop
• Loop cutting by control points

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X
0
1
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Memory test schemes

• Black boxing
• space compactors can be used on inputs
• multiplexing or gating on the output
• driven by flip-flops and MTPI

• Transparency

• Bypass

Memory block
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Uncontrollable clocks
Test mode
Clock
Make them controllable in test mode!
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Pseudo-random testing

• Though generated deterministically, test vectors
  have the characteristics of random patterns
• Applicable to both combinational and sequential
  circuits
• Fault simulation is required
• No test data to store
• Tests generated by very simple hardware
• Applicable to BIST
• Must be supplemented by other techniques if
  random-pattern-resistant faults occur

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Random pattern resistance
20 - 40 of faults are typically random pattern
resistant
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Example of RPR
Only one out of 232 (4 billion) patterns detects
the fault
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Test points - control points

• Types of control points
• AND - enhance controllability of 0
• OR - enhance controllability of 1
• XOR - balance control of 0 and 1 without
  reducing observability
• Source of stimuli
• generator of test patterns - pseudorandom and
  switching independently
• additional scan cells - pseudorandom and
  switching independently
• phase decoder - quasistatic and strongly
  correlated

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AND and OR control points
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Control points driven by scan
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Multiphase test point insertion (MTPI)
D
C4
C
C3
B
C2
A
Phase C1 C2 C3 C4 Test 0 0 0 0 0 - 1 0 1 1 1 A
2 1 0 1 1 B 3 1 1 0 1 C 4 1 1 1 0 D
C1
Pattern counter
0
4
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MTPI architecture
Phase decoder
100
Fault coverage
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Logic off-limits to control points

• Critical paths
• Bus one-hot encoding logic for buses
• Outputs of large drivers
• Bounding logic

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STUMPS architecture
COMPA C T O R
T E S T G E N E R A T O R

scan chains
Control
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Logic BIST architecture - MTPI
...
Scan
Scan
...
...
Scan
Sen
Hold /Reset
Hold /Reset
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Logic BIST architecture - TPI
...
Scan
Scan
P H A S E S H I F T E R
...
...
Scan
Sen
Hold /Reset
BIST controller
Hold /Reset
Done
Clock
Run
Reset
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BIST session
Scan
...
Scan
Reset
Hold
Reset
Hold
SC
0
128
Sen
PC
1
Clock
Clock
loading
unloading
Sen
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Simple BIST controller
Sin
Sout
Sen
Scan
...
...
Sen
Scan
Shift counter
BIST Run
BIST Done
hold
Pattern counter
Clock
BIST Reset
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BIST controller and TAP
Sin
Sout
Sen
Scan
P R P G
...
...
Sen
Scan
Shift counter
hold
Pattern counter
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Boundary scan and BIST
Boundary scan
Load BIST registers RUNBIST Unload MISR
Application logic
TDI
Device ID register
BR
Instruction decoder
TDO
Output buffer
Instruction register
TMS
TAP
TCK
TRST
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Signature comparison
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Handling of primary inputs
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Handling of primary outputs
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Logic BIST flow
SCAN
Test Points
X-Bound
final core netlist
Gate level netlist
Time-based Simulations
RTL to Gates
BIST Controller Synthesis
RTL for controller
Parallel Pattern Simulator
Fault coverage reports
Verilog / VHDL testbench
PRPG and MISR values per pattern
Testbench Test Vector Generation
Scan chain load/ unload data
ATE
WGL vectors
results
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Diagnostics - overview

• Use bypass mode and conventional ATPG
• Different pattern set for ATPG versus diagnostics
• Use only MISR values to diagnose fault
• Minimal data volume
• complex algorithms to isolate failing gates
• Must deal with MISR corruption
• Hybrid techniques
• MISR value is used to identify failing pattern
• BYPASS mode unloads subset of failing patterns

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Diagnostics- hybrid approach
Run pass/fail test
Check MISR
128k patterns
Identify failing pattern regions
...
8k patterns
Check MISR
8k patterns
Check MISR
8k patterns
Check MISR
Identify individual failing patterns
8k patterns with MISR re-load after each pattern
Unload a subset of failing patterns
Seed PRPG, apply pattern unload scan data
Seed PRPG, apply pattern unload scan data
Seed PRPG, apply pattern unload scan data
...
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TI Results
ASIC-1
ASIC-1
ASIC-1
ASIC-1
125MHz 65K 96.0 3.4 0.1s 0.6h 0.9h
At-speed test ? BIST pattern count BIST
stuck-at grade BIST gate overhead BIST
silicon run time Delta RTL to gates Fault
simulation time
75MHz 262K 95.7 2.6 0.6s 3.0h 3.4h
75MHz 262K 95.3 2.1 0.9s 6.0h 5.2h
75MHz 262K 95.6 1.6 1.2s 13.4h 4.0h
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Other results
Size
Speed
Coverage
patterns
90K
ARM Core
?
Over 95
32K
200 ctrl points, 200 observe points
Size
Speed
Coverage
patterns
1250K
Cisco Telecom Design
62.5MHz
96.15
16K
(ITC 2001)
967 ctrl points, 1000 observe points
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Summary

• BIST-able design should have
• scan
• no internal bus conflicts or floating buses
• no X states propagating to observable outputs
• be random-pattern testable
• X states are bounded by test logic
• Random pattern testability is improved by control
  and observe points
• ATPG patterns may be used to achieve the highest
  possible coverage