State of the Art Architectures Xilinx and Altera

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State of the Art ArchitecturesXilinx and Altera

• Mark L. Chang
• ACME Seminar
• June 30, 2003

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The Timeline

• 1998 Xilinx Virtex
• 1999 Xilinx Virtex-E
• 2000 Xilinx Virtex-II
• June 2000
• Altera Nios soft-core processor ships
• Excalibur announced

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The Timeline

• Sept. 2000
• Excalibur architecture unveiled
• April 2001
• Xilinx MicroBlaze soft-core processor ships
• October 2001
• Excalibur ships

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The Timeline

• February 2002
• Altera Stratix announced
• March 2002
• Xilinx Virtex-II Pro ships
• June 2002
• Stratix ships

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Head-to-Head

• Xilinx Virtex-II Pro
• 1.5v 130nm copper
• 125,136 logic cells
• 10Mb RAM
• 556 18x18 multipliers
• Up to four PowerPC 405 cores

• Altera Stratix
• 1.5v 130nm copper
• 114,140 logic elements
• 10Mb RAM
• 224 9x9 multipliers
• No hard processor cores (Excalibur, based on Apex
  20k)

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Xilinx Virtex-II Pro
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Altera Stratix
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Xilinx Virtex CLB
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Virtex Slice
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Half Slice
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3-State Buffers
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Altera Stratix
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Logic Array Blocks (LABs)
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Logic Element
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Embedded RAM

• Xilinx Block SelectRAM
• 18Kb dual-port RAM arranged in columns
• Altera TriMatrix Dual-Port RAM
• M512 512 x 1
• M4K 4096 x 1
• M-RAM 64K x 8

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Xilinx Embedded Multipliers
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Altera Embedded DSP Blocks

• Two DSP Block columns per device
• Number varies by height of column
• Can implement
• Eight 9x9 multipliers
• Four 18x18 multipliers
• One 36x36 multiplier
• Contains adder/subtracter/accumulator
• Registered inputs can become shift register

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Altera Multiplier Sub-block
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Virtex Active Interconnect
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Virtex Hierarchical Interconnect
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Altera MultiTrack Interconnect

• Direct link between LABs and adjacent blocks
• Row interconnects
• 4, 8, and 24 blocks left or right
• Column interconnects
• 4, 8, and 16 blocks up or down

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Stratix R4 Interconnect
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Big Differences

• Xilinx
• 3DES bitstream decrypter on-board
• RocketIO serial transceivers
• Partial reconfiguration
• Altera
• Documented self-reconfiguration in Excalibur

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Xilinx MicroBlaze
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Altera Nios
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Virtex PowerPC Core
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PowerPC 405

• Five-stage pipeline
• Independent instruction and data caches
• 16KB two-way set associative (256 x 32B)
• Write-back or write-through data cache
• Static branch prediction
• Real memory management unit
• TLB, memory protection
• 300MHz, 420 MIPS

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Interface to Virtex

• On-Chip Memory Controller (OCM)
• Interface between PowerPC core and BRAM
• Separate data and instruction OCMs
• Scratch-pad memory
• Bi-directional data transfer to FPGA blocks
• Storage is interrupt service routines
• Processor Local Bus

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Processor Local Bus
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Excalibur ARM Core
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ARM 922T

• Single stripe embedded in Apex 20K
• Five-stage pipeline
• 8KB 64-way set-associative instruction and data
  caches
• 256KB internal single-port SRAM
• 128KB internal dual-port SRAM
• All FPGA interface through ABMA buses

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ARM922T Stripe
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Head-to-Head

• Implement 97 customer designs
• Sizes up to 61,000 LEs
• Basic unit of comparison LE
• 4-LUT, register, and anything else associated
• 80 are more efficient on Altera
• Uses on average 9 fewer LEs
• 41 are gt10 more efficient

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Logic Utilization
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DSP Block vs. 18x18 MUL
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Memory Comparison
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Lattice Semiconductor ispXPGA

• E2CMOS built-in to FPGA die stores configurations
• Non-volatile, but still SRAM-based for infinite
  reconfigurability
• Four 4-LUTs per block
• Two flip-flops per 4-LUT
• Small embedded RAMs

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ispXPGA
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Actel ProASIC
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Actel ProASIC