CS 140 Lecture 9 Sequential Networks

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CS 140 Lecture 9Sequential Networks

• Professor CK Cheng
• CSE Dept.
• UC San Diego

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Sequential Networks
Combinational
D
B
C
A
CLK
CLK

• Components F-Fs
• Specification
• Implementation Excitation Table

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Specification

• Finite State Machine
• Input Output Relation
• State Diagram
• State Table
• Circuit
• Logic Diagram
• Netlist
• Boolean Expression

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Netlist ? State Table ? State Diagram? Input
Output Relation
y(t) Q1(t)Q0(t) Q0(t1) D0(t)
x(t)Q1(t) Q1(t1) D1(t) x(t) Q0(t)
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Netlist ? State Table ? State Diagram? Input
Output Relation
x
D1
Q1
Q0
Q
D
Q
y
Q
D
Q0
Q1
Q
D0
Clk
y(t) Q1(t)Q0(t) Q0(t1) D0(t)
x(t)Q1(t) Q1(t1) D1(t) x(t) Q0(t)
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Logic Diagram gt State Table
y(t) Q1(t) Q0(t) Q0(t1) D0(t) x(t)
Q1(t) Q1(t1) D1(t) x(t) Q0(t)
State table
input
Let S0 00 S1 01 S2 10 S3 11
x0 x1
PS
0 0 0 1 1 0 1 1
00, 0 10, 0 10, 0 10, 0 00, 0 11, 0 10, 1
11, 1
Q1(t) Q0(t) Q1(t1) Q0(t1), y(t)
Remake the state table using symbols instead of
binary code , e.g. 00
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State Table gt State Diagram
Example Output sequence
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Example with T Flip-Flops
y(t) Q1(t)Q0(t) Q0(t1) T0(t) x(t)
Q1(t) Q1(t1) T1(t) x(t) Q0(t)
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Logic Diagram gt Excitation Table gt State Table
y(t) Q1(t)Q0(t) T0(t) x(t) Q1(t) T1(t)
x(t) Q0(t) Q0(t1) T0(t) Q0(t)T0(t)Q0(t) Q
1(t1) T1(t) Q1(t)T1(t)Q1(t)
Excitation Table
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Excitation Table gtState Table gt State Diagram
State Assignment S0 00 S1 01 S2 10 S3 11
1/1
0/0
0/1
S0
S1
S3
0, 1/0
1/0
S2
1/0
0/0
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Excitation Table gtState Table gt State Diagram
Example Output sequence
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Implementation State Diagram gt State Table gt
Netlist
Pattern Recognizer A sequential machine has a
binary input x in a,b. For x(t-2, t) aab, the
output y(t) 1, otherwise y(t) 0.
b/1
b/0
S1
S0
a/0
a/0
S2
a/0
b/0
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State Diagram gt State Table with State Assignment
State Assignment S0 00 S1 01 S2 10
Q1(t1)Q0(t1), y
a 0 b 1
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State Table gt Excitation Table
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Excitation Table gt Boolean Expression
D1(t) xQ0 xQ1 D0 (t) Q1Q0 x y Q1x
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Q0
Q1
D0
Q
Q0
D
x
Q
Q1
y
x
D1
Q
D
Q0
Q
Q1
x
D1(t) xQ0 xQ1 D0 (t) Q1Q0 x y Q1x
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Canonical Form Mealy and Moore Machines
x(t)
y(t)
Combinational Logic
CLK
C2
x(t)
y(t)
x(t)
C1
C2
y(t)
C1
CLK
CLK
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Canonical Form Mealy and Moore Machines
Moore Machine yi(t) fi(X(t), S(t)) Mealy
Machine yi(t) fi(S(t)) si(t1) gi(X(t),
S(t))
x(t)
x(t)
C1
C2
y(t)
C1
C2
y(t)
CLK
CLK
s(t)
s(t)
Moore Machine
Mealy Machine
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Finite State Machine Example

• Traffic light controller
• Traffic sensors TA, TB (TRUE when theres
  traffic)
• Lights LA, LB

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FSM Black Box

• Inputs CLK, Reset, TA, TB
• Outputs LA, LB

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FSM State Transition Diagram

• Moore FSM outputs labeled in each state
• States Circles
• Transitions Arcs

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FSM State Transition Diagram

• Moore FSM outputs labeled in each state
• States Circles
• Transitions Arcs

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FSM State Transition Table

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State Transition Table

Q1(t1) Q1(t)Å Q0(t) Q0(t1) Q1(t)Q0(t)TA
Q1(t)Q0(t)TB
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FSM Output Table
LA1 Q1 LA0 Q1Q0 LB1 Q1 LB0 Q1Q0
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FSM Schematic State Register
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Logic Diagram
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FSM Schematic Output Logic