Graphbased Functional Test Program Generation for Pipelined Processors

1
Graph-based Functional Test Program Generation
for Pipelined Processors

• Prabhat Mishra Nikil Dutt
• Center for Embedded Computer Systems
• University of California, Irvine, USA

2
Outline

• Motivation
• Related Work
• Functional Test Generation
• A Case Study
• Conclusion

3
Introduction

• Functional verification is a major bottleneck
• of logic bugs is increasing at 3-4x /
  generation
• Micro-architectural complexity largest
  contributor
• Larger design teams ? more communication gap
• Requires complementary validation techniques

4
Traditional Validation Approach
Architecture Specification (English Document)
Specification
Model Checking
Verification
Formal
Abstracted Design
Implementation
Abstraction
RTL Design
Simulation
Uses a combination of simulation techniques and
formal methods
5
Motivation

• Existing Validation Techniques
• Bottom-up methodology
• Lack of a golden reference model
• Difficult to find micro-architectural bugs
• Uses reverse-engineering (abstraction) methods
• Specification has all the details
• Lack of a comprehensive coverage metric
• Code coverage, FSM coverage, not sufficient
• Need for a functional coverage metric
• Our Approach
• A top-down validation methodology
• Language-based architecture specification
• Functional coverage based on pipeline
  interactions
• Specification-driven functional test generation
• Complements existing bottom-up techniques

6
Outline

• Motivation
• Related Work
• Functional Test Generation
• A Case Study
• Conclusion

7
Related Work

• Directed test program generation
• Aharon et al., DAC 1995
• Shen et al., DAC 1999
• Pipeline behavior is not considered
• Test generation for pipelined processors
• Ur and Yadin, DAC 1999
• Iwashita et al., ICCAD 1994
• Campenhout et al., DAC 1999
• No coverage metric for pipeline interactions
• Functional test program generation
• Chen et al., DAC 2003, Lai and Cheng, DAC 2001
• Applied in the context of manufacturing testing

8
Outline

• Motivation
• Related Work
• Functional Test Generation
• A Case Study
• Conclusion

9
Functional Validation of Pipelined Processors
Test Generator
Pipelined Processor
TestGen
MOV R1, 011 MOV R2, 010 ADD R3, R1, R2 R3 101
Test Program
R3 101 ?
Check Result
Verifies the functionality of the processor using
assembly programs
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Functional Test Program Generation

• Processor model
• Graph model for pipelined processors
• Functional fault model
• Pipeline interactions based on graph coverage
• Coverage-directed test generation technique
• Model checker to generate test programs
• write the negation of the property to be verified
• model checker generates example to disprove
  (counter-example)

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Test Generation Methodology
Architecture Specification
ADL Specification
Simulator Generation
SMV
Not Enough Properties
Counterexamples
Coverage Report
Simulator
Automatic
ADL Architecture Description Language
Manual
Test Programs
Feedback
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Test Generation Example

• Initialize registers Ain and Bin with values 2
  and 3 at cycle 9

One property assert G ((cycle8) ? X ((DIV.Ain
2) (DIV.Bin 3))) Apply at processor
level needs 375.98 sec. and 1928568 BDD nodes
using 333 MHz Sun with 128M RAM
Problem Test generation is limited by the
capacity restrictions of the tool.
Solution Apply properties at the module level
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Modified Test Generation Methodology
Properties are applied at the module level
SMV Description (for node N)
Property (for node N)
SMV
N parent of N
N parent of N
Counterexamples
input assignments
primary i/p?
output req. for parent node
yes
Simulator
coverage report
test programs
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Test Generation Example

• Example Initialize Ain and Bin with values 2 and
  3 at cycle 9

• Apply to DIV unit
• assert G ((cycle8) ? X((Ain 2) (Bin 3)))
• input assignments divInst.src1 2, divInst.src2
  3
• Apply to Decode unit
• assert G((cycle7) ? X((divInst.src1 2)
  (divInst.src2 3)))
• input assignments oper DIV R3 R1 R2 RF12,
  RF23
• Apply to Fetch unit
• assert G((cycle6) ? X(oper.opcode DIV)
  (oper.src1 1) (oper.src2 2)))
• input assignments PC5, Memory5 DIV R3 R1 R2

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Final Test Program Example
Fetch Cycle Opcode Dest Src1 Src2
1 NOP 2
ADDI R1 R0 2 3
ADDI R2 R0 3 4
NOP 5 NOP 6
NOP 7 DIV
R3 R1 R2

• Using our modified methodology
• requires 1 sec. and 5600 BDD nodes
• 333 MHz Sun UltraSparc II with 128M RAM
• When applied at the processor level
• requires 375.98 sec. and 1928568 BDD nodes
• An order of magnitude improvement time/space

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Outline

• Motivation
• Related Work
• Functional Test Generation
• Processor Specification
• Model Generation
• Functional Coverage
• Coverage-driven Test Generation
• A Case Study
• Conclusion

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Processor Specification

• Use Architecture Description Language (ADL)
• EXPRESSION ADL
• Pipelined processor architectures
• Captures both structure and behavior
• Structure components and their connectivity
• Behavior instruction set of the architecture
  (ISA)
• The ADL is used for exploration, synthesis,
• Public release http//www.ics.uci.edu/express

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Specification of the DLX Processor
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
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Specification of the DLX Processor
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
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Specification of the DLX Processor
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
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Specification of the DLX Processor
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
22
Specification of the DLX Processor
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
23
Specification of the DLX Processor
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
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Specification of the DLX Processor
Structure
Behavior
(OPCODE ADD (OPERANDS (SRC1 rf) (SRC2 imm)
(DEST rf)) (BEHAVIOR DEST SRC1 SRC2)
(FORMAT ) )
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Specification of the DLX Processor
Structure
Behavior
(OPCODE ADD (OPERANDS (SRC1 rf) (SRC2 imm)
(DEST rf)) (BEHAVIOR DEST SRC1 SRC2)
(FORMAT ) )
Mapping
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Outline

• Motivation
• Related Work
• Functional Test Generation
• Processor Specification
• Model Generation
• Functional Coverage
• Coverage-driven Test Generation
• A Case Study
• Conclusion

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Pipelined Processor Model
Graph Model
Graph (Nodes, Edges) Nodes units U
storages Edges data-transfer edges U
pipeline edges
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Processor Model Generation

• Used Functional Abstraction Technique
• Defined generic functions, sub-functions using
  SMV
• Compose functions to generate new architecture

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Outline

• Motivation
• Related Work
• Functional Test Generation
• Processor Specification
• Model Generation
• Functional Coverage
• Coverage-driven Test Generation
• A Case Study
• Conclusion

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Functional Coverage

• When to end the verification effort?
• Code coverage, toggle coverage, fault coverage
• No direct relation with device functionality
• We propose a functional coverage metric
• Based on coverage of pipeline interactions
• Measures interactions between instructions and
  pipeline stages through graph coverage
• Used for test program generation

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Functional Fault Model
Fetch
MEM
1. Node Fault A node does not execute
correctly - active - stalled -
exception - flushed 2. Edge Fault An
edge does not transfer inst./data correctly
- active - stalled - flushed 3.
Pipeline Fault Incorrect execution due to
multiple faults - two simultaneous node/edge
faults
Decode
ALU
AddrCalc
RF
LdSt
WB
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Outline

• Motivation
• Related Work
• Functional Test Generation
• Processor Specification
• Model Generation
• Functional Coverage
• Coverage-driven Test Generation
• A Case Study
• Conclusion

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Coverage-directed Test Generation

• Algorithm
• Inputs
• 1. Graph Model of the processor, G
• 2. List of possible faults, faultList
• Output Test programs for detecting all the
  faults in the fault model
• begin
• TestProgramList
• for each fault in the faultList
• testprogreg createTestProgram(fault , G)
• TestProgramList TestProgramList U testprogreg
• endfor
• return TestProgramList
• end

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Coverage-directed Test Generation
Fetch

• Example generate test to make edge LdSt-ALU
  active
• Two properties need to be generated
• Make the node LdSt active at clock cycle t
• Make the node ALU active at clock cycle (t1)
• Test Program
• LOAD R1, R5, 0x1
• NOP
• MOV R3, R1

Decode
AddrCalc
ALU
RF
Memory (latency 1)
LdSt
WB
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Outline

• Motivation
• Related Work
• Functional Test Generation
• A Case Study
• Conclusion

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A Case Study

• The Architecture
• DLX Processor
• 20 nodes
• 24 edges
• 91 instructions

Unit
Storage
Pipeline edge
Data-transfer edge
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Experiments

• DLX processor 20 nodes, 24 edges, 91
  instructions
• 223 test programs needed to cover all single
  faults
• Reduction possible - 43 test programs
• Random/constrained-random techniques requires an
  order of magnitude more test programs to cover
  these faults.

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Conclusions

• Functional validation is a major bottleneck
• We presented a specification-driven test
  generation technique
• Language-based specification of the processor
• Automatic graph model generation
• Functional coverage based on pipeline
  interactions
• Coverage-directed test generation
• Reduces required BDD size, test generation, and
  test application time by an order of magnitude
• In future, apply this methodology for functional
  validation of real-world pipelined processors

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Thank you