UDP Device Peripheral

1
UDP Device Peripheral
2
Objectives

• Understand the UDP initialization
• Understand the USB schematics
• Overview of UDP registers
• Understand how to handle USB packets
• Highlight UDP pitfalls

3
UDP block diagram

• Connected to ASB
• 2 clocks MCK 48MHz
• No DMA
• Embedded transceiver
• General purpose endpoints

4
Device USB driver components
USB Device driver API

• Control Protocol
• Standard Requests
• Class Requests
• Vendor Requests

• Endpoint Data
• Transfer ProtocolsBulk In/Out
• Isochronous In/Out
• Interrupt In/Out

PowerManagement
StatusControl
Pull-UpResistor
ClockRegisters
USB ControllerRegisters
5
UDP Power Management

• The UDP requires 2 clock sources MCK UDPCK
• MCK is required for register read/write
  operationsAT91C_BASE_PMC-gtPMC_PCER (1 ltlt
  AT91C_ID_UDP)
• UDPCK is required when the UDP shall
  communicatesAT91C_BASE_PMC-gtPMC_SCER
  AT91C_PMC_UDP
• The bit time defined in the USB V2.0 spec is
  12Mbps (2500ppm)
• UDPCK must be configured at 48MHz /-0.25
• UDPCK is derived from PLL output or PLLoutput /
  2AT91C_BASE_CKGR-gtCKGR_PLLR
  AT91C_CKGR_USBDIV_1
• In power mode and suspend mode MCK and UDPCK can
  be switched off
• Reset and resume events are detected
  asynchronously

6
Attach/Detach pull-up

• When the host is switched off, a bus powered
  device must not supply the host through the
  pull-up resistor
• Timing
• When the device is bus-powered, the pull-up must
  be connected within 100ms after the device starts
  to drain current on Vbus.
• Once the pull-up is active, the device has 100ms
  to be able to answer to the first request

• Pull-up can be connected between DP and 3.3V,
  but
• The startup time must be less than 150ms
• 3.3V must be derived from VBus

7
Attach/Detach pull-down

• When the peripheral is not connected, DP may be
  connected to 3.3V through the pull-up, DM is
  floating gt over consumption.
• The solution is to connect a pull-down while the
  pull-up is not active

• If the pull-down is integrated in the
  transceiver, then the pull-down is automatically
  connected when the pull-up is disconnected.AT91C_
  BASE_UDP-gtUDP_TXVC AT91C_UDP_PUON
• If the pull-down is not integrated, then
• A pull-down controlled by a PIO can be added to
  the PCB
• Or a 300KOhms pull-down can be added without
  control gt 100uA when the UDP is driving a K
  state

8
Attach/Detach transceiver enable

• When the transceiver is disabled, consumption is
  reduced
• End of bus reset and resume are asynchronously
  detected even if the transceiver is disabled.
• When transceiver enable is controlled by
  software, the application must enable the
  transceiver before any transmissions.

• On some AT91parts, by default at reset
  transceiver is enabled. To reduce power
  consumption, it must be disabled.AT91C_BASE_UDP-gt
  UDP_TXVC AT91C_UDP_TXVDIS
• Beware UDP periph clock must be enabled before
  write operation to the UDP_TXVC clock

9
Attach/Detach pull-up

• SAM9261 transceiver disable and pull-up enable
  are located in the special function register of
  the HMATRIX.
• SAM9261 the transceiver is disabled after
  reset.
• SAM7SE new parts integrate most of the discrete
  components required to match the USB
  specification.

10
AT91RM9200 schematics
5V Vbus monitoring
1.5K
Pull-up is active by default after reset

• Pull-up is active by default after reset
  (required by the boot application)
• No pull-down DM is floating when the peripheral
  is disconnected
• The application shall monitor Vbus to remove the
  pull-up when the host switches off

11
AT91SAM7S schematics
PIO
1.5K
DP
PIO

• Pull-up is automatically removed when the host
  switches off
• The application must enable the pull-up using a
  PIO
• No pull-down DM and DM are floating when the
  host is disconnected

12
SAM7A3 schematics
DP
VBus
DM

• DP pull-up is connected as soon as the board is
  powered
• Safer ESD protections
• Could not be used with integrated pull-up
• Serial resistor may not be good
• DM is floating

13
SAM9260 Schematics
VBus
15K
Vbus detect
22K
39 Ohms
DP
39 Ohms
DP

• Pull-up and pull-down are integrated
• Vbus monitoring is done through a PIO
• Pull-up is under application control
• After reset the pull-up is disabled

14
Suspend mode

• In suspend mode, the power consumption for the
  peripheral must be less then 500uA.
• 200uA are drained by the 1.5K resistor
• Time to enter in suspend mode 7ms
• Time to wake-up mode 10ms

• In suspend mode
• Transceiver is disabled
• UDP periph clock and 48MHz can be switched off
• To wake-up
• Resume event is asynchronously detected (an IT is
  generated)
• UDP periph clock and 48 MHz must be enabled
• THEN transceiver can be enabled

15
UDP initialization

• Very few things can be done during the
  initialization
• Configure and enable UDP interrupt in the AIC
• Enable 1.5K pull-up
• Enable the UDP
• // Configure interrupts
• AT91F_AIC_ConfigureIt(
• AT91C_BASE_AIC,
• AT91C_ID_UDP,
• AT91C_AIC_PRIOR_LOWEST,
• AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE,
• AT91F_Udp_Handler)
• AT91F_AIC_EnableIt(AT91C_BASE_AIC,
  AT91C_ID_UDP)
• // Clear to set the Pul up resistor
• AT91F_PIO_ClearOutput(AT91C_BASE_PIOA,AT91C_PIO_P
  A16)
• // Enable the UDPAT91C_BASE_UDP-gtUDP_FADDR
  AT91C_UDP_FEN
• The host detects the pull-up and starts the
  communication forcing a bus reset state on the
  line.
• At the end of the reset, an interrupt
  UDP_ENDBUSRES is triggered.
• The device has 10 ms to enable UDP clocks before
  it accepts the first UDP transfer.

16
Global interrupts

• Following bus events are asynchronously detected
  by the macro
• End of bus reset (UDP_ENDBUSRES)
• Wakeup (UDP_WAKEUP)
• These events generate an interrupt which can not
  be masked in the UDP peripheral. They can be in
  the AIC.
• Other events are maskable
• SOF interrupt trigs every ms while the host is
  not in suspend mode
• Interrupts must be acknowledged by writing to the
  UDP_ICR register

17
Basic Interrupt Service Routine

• unsigned int interrupt Udp_get_flag(pUdp,
  UDP_ISR) Udp_get_flag(pUdp, UDP_IMR)
• while (interrupt ) if (interrupt
  AT91C_UDP_ENDBUSRES) //! - Handle End Of Bus
  Reset ...
• //! - Acknowledge the IT
• Udp_set_flag(pUdp, UDP_ICR, AT91C_UDP_ENDBUSRES
  )
• else if (interrupt AT91C_UDP_RXRSM)
• //! - Handle Resume
• ...
• //! - Acknowledge the IT
• Udp_set_flag(pUdp, UDP_ICR, AT91C_UDP_RXRSM)
• else
• for (i 0 i lt 8 i)
• if (interrupt (1 ltlt i))
• udp_endpoint_handler(pUdp, i)
• Udp_set_flag(pUdp, UDP_ICR, (1 ltlt i))
• interrupt Udp_get_flag(pUdp, UDP_ISR)
  Udp_get_flag(pUdp, UDP_IMR)

18
End Of Bus Reset operations

• After an end of bus reset, has been detected, the
  application must
• Configure the PLL at 48MHz or 96MHz
• Enable MCK AT91C_BASE_PMC-gtPMC_PCER (1 ltlt
  AT91C_ID_UDP)
• Enable UDPCK AT91C_BASE_PMC-gtPMC_SCER
  AT91C_PMC_UDP
• Configure endpoint 0
• Acknowledge the interruptAT91C_BASE_UDP-gt
  UDP_ICR, AT91C_UDP_ENDBUSRES

19
Controlling device states

• The device enters address state at the end of the
  status stage
• The device address is set in the FADD field of
  the UDP_FADDR register
• The device state is updated after a setAddress
  and a setConfiguration request in the
  UDP_GLB_STAT register

20
Endpoints configuration

• Endpoints are reset by writing to the UDP_RST_EP
  register
• Beware this is a 2 step operationAT91C_BASE_UDP-
  gtUDP_RST_EP ( 1 ltlt endpoint)AT91C_BASE_UDP-gtUD
  P_RST_EP 0
• Endpoints are configured by writing the EPTYPE
  field in the corresponding UDP_CSR
  registerAT91C_BASE_UDP-gtUDP_CSRendpoint
  AT91C_UDP_EPTYPE_CTRL// Could have been
  // AT91C_UDP_EPTYPE_ISO_IN, AT91C_UDP_EPTYPE_ISO_
  OUT// AT91C_UDP_EPTYPE_BULK_IN,
  AT91C_UDP_EPTYPE_BULK_OUT// AT91C_UDP_EPTYPE_INT_
  IN, AT91C_UDP_EPTYPE_INT_OUT
• Endpoints are enabled by setting EPEDS in the
  corresponding UDP_CSR register
  AT91C_BASE_UDP-gtUDP_CSRendpoint
  AT91C_UDP_EPEDS

21
Endpoint interrupts

• 5 endpoint events can trig an endpoint interrupt.
• RXSETUP A setup packet has been received during
  a control transfer
• TXCOMP A data packet has been sent to the host.
  The host has sent an acknowledge.
• RX_DATA_BK0, RX_DATA_BK1 A data packet has been
  received from the host.
• STALL_SENT A stall packet has been sent to the
  host
• The interrupt is cleared by clearing the
  corresponding flag in the UDP_CSR register.

22
Endpoint control

• Endpoint control is done writing to the
  corresponding UDP_CSR register.
• TXPKTRDY a packet has been written to the FIFO
  and is ready to be sent
• FORCESTALL answer a stall packet to the host
• DIR (for control endpoint only) fix the
  direction of the data stage

• UDP_CSR is used as a configuration register,
  status register and control register.
• Due to synchronization issues, it is mandatory to
  check between successive set or clear flag that
  the operation has been taken into account by
  reading the UDP_CSR register. Otherwise this may
  lead to unexpected behavior.
• //! Set flags of UDP UDP_CSR register and waits
  for synchronization
• define Udp_ep_set_flag(pUdp, endpoint, flags)
  \
• while ( (pUdp-gtpInterface-gtUDP_CSRendpoint
  (flags)) ! (flags) ) \
• pUdp-gtpInterface-gtUDP_CSRendpoint
  (flags) \

23
Endpoint FIFOs

• A FFIFO is associated with each endpoint. It
  contains a data payload received or to be sent.
• FIFO access is performed through the
  corresponding UDP_FDR register.
• UDP_FDR is an 8 bit ASB register
• Some FIFO are dual bank FIFO
• FIFO size and single or dual bank feature are
  defined in the datasheet.

24
FIFO transfers

• Transfers are usealy done in the ISR.
• Transfers can be improved using the following
  routine which unfolds the loops

MACRO AT91C_UDP_WR_8 scratch, fdr,
base ldrb scratch, base, 1 str
scratch, fdr MEND
25
Dual bank FIFOs

• Dual Bank FIFOs are mandatory for isochronous
  transfer
• Dual Bank FIFOs improve bulk transfer bandwidth
• Dual Bank FIFOs can not be used for control
  transfer
• Dual Bank FIFOs for write operation
• The application pushes data in a bank while the
  UDP sends the other bank
• Dual Bank FIFOs for read operation
• The application pops data from a bank while the
  UDP receives the other bank

26
Setup transaction

• receives a RXSETUP interrupt on endpoint 0
• reads the data from the FIFO UDP_FDR0
• sets the DIR bit if required in the UDP_CSR0
• clears RXSETUP in the UDP_CSR0
• clears EP0 interrupt in the UDP_ICR

• The application

27
Data Out Transaction (single bank)

• The application

• receives a RX_DATA_BK0 interrupt on endpoint x
• reads the data from the FIFO UDP_FDRx
• clears RX_DATA_BK0 in the UDP_CSRx
• clears EPx interrupt in the UDP_ICR

28
Data Out Transaction (dual bank) (1)
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Data Out Transaction (dual bank) (2)

• The application

• receives a RX_DATA_BK0/BK1 interrupt on endpoint
  x
• reads the data from the FIFO UDP_FDRx
• clears RX_DATA_BK0/BK1 in the UDP_CSRx
• clears EPx interrupt in the UDP_ICR

• If it requires a long time for the application to
  enter in the ISR then RX_DATA_BK0 and RX_DATA_BK1
  can be both set.
• The application must maintain an internal counter
  to know which flag must be cleared first.
• Clearing the wrong flag leads to unexpected
  results.

30
Data Out Transaction (dual bank) (3)
//-----------------------------------------------
----------------------------- //! \fn
udp_get_rx_flag //! \brief This function returns
the flag to be cleared //------------------------
--------------------------------------------------
-- static unsigned char udp_get_rx_flag(S_udp_endp
oint pEndpoint) unsigned int clrFlag
pEndpoint-gtclrFlag if (pEndpoint-gtnbBanks gt 1)
if (pEndpoint-gtclrFlag AT91C_UDP_RX_DATA_BK
0) pEndpoint-gtclrFlag AT91C_UDP_RX_DATA_BK1
else pEndpoint-gtclrFlag
AT91C_UDP_RX_DATA_BK0 return clrFlag
31
Data In Transaction (Single Bank)

• writes data to the FIFO UDP_FDRx
• Sets TXPKTRDY in the UDP_CSRx
• Once the packet has been acknowledged by the host
• Receives a TXCOMP interrupt on endpoint x
• Clears TXCOMP
• clears EPx interrupt in the UDP_ICR

• The application

32
Data In Transaction (Dual Bank) (1)
33
Data In transaction (Dual Bank) (2)

• The application

• writes a first data payload to the Fifo
  UDP_FDRx
• Sets TXPKTRDY in the UDP_CSRx
• Writes a second data payload to the
  FifoUDP_FDRx
• Once the packet has been acknowledged by the host
• Receives a TXCOMP interrupt on endpoint x
• Clears TXCOMP
• Set TXPKTRDY in the UDP_CSRx
• Writes a third data payload to the
  FifoUDP_FDRx
• clears EPx interrupt in the UDP_ICR

• The application needs to implement a small state
  machine to know how many banks are currently used

34
Data In transaction (Dual Bank) (3)

• if (csr AT91C_UDP_TXCOMP)
• Udp_ep_clr_flag(pUdp, endpoint,
  AT91C_UDP_TXCOMP)
• switch (Udp_get_state(pEndpoint))
• case UDP_WRITE0
• //! - If this is the last packet, invoke the
  callback
• Udp_eot(pEndpoint, USB_STATUS_SUCCESS)
• break
• case UDP_WRITE1
• //! - Else if this is the last one or if we
  work on a single bank endpoint write one packet
• pEndpoint-gtindex udp_write_payload(pUdp,
  pEndpoint, endpoint)
• Udp_ep_set_flag(pUdp, endpoint,
  AT91C_UDP_TXPKTRDY)
• if (pEndpoint-gtindex pEndpoint-gtlength)
• Udp_set_state(pEndpoint, UDP_WRITE0)
• break
• case UDP_WRITE2
• //! - Else if double bank trig the
  transmission of the current bank and prepare the
  next packet to be sent
• Udp_ep_set_flag(pUdp, endpoint,
  AT91C_UDP_TXPKTRDY)
• if (pEndpoint-gtindex lt pEndpoint-gtlength)
• pEndpoint-gtindex udp_write_payload(pUdp,
  pEndpoint, endpoint)

35
Objectives

• Understand the UDP initialization
• Understand the USB schematics
• Overview of UDP registers
• Understand how to handle USB packets
• Highlight UDP pitfalls