CSET 4650 Field Programmable Logic Devices

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CSET 4650 Field Programmable Logic Devices
Introduction to PLAs Programmable Logic Arrays

• Dan Solarek

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Programmable Logic Array (PLA)

• Introduced in 1975
• Predates the invention of the PAL
• The first PLD
• The most user-configurable of the traditional
  two-level programmable logic devices

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Programmable Logic Array (PLA)

• A PLA is a large 2-level AND / OR array with lots
  of inputs and product terms
• Most general/flexible device of this architecture
• PROM, PAL, PLA
• Programmable connections for both AND / OR
• Uses the sum of products (SOP) form

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PLA Block Diagram

• Same 2-level AND/OR logic arrangement as with
  PROM and PAL devices

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PLA Description

• the third simple PLD we will study
• decode only some of the input addresses (PROMs
  decoded all of them)
• increased propagation delay because of both the
  AND and OR array inputs are programmable
• naming convention not as systematic as PALs
• also called FPLAs

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PLA A More General Idea
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Programmable Logic Array (PLA)

• n input variables
• AND gates have 2n inputs
• true and inverted form of each input variable
• m outputs
• driven by large OR gates
• each AND gate is programmably connected to each
  outputs OR gate (shareable product terms)

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Nomenclature 4x6x3 PLA
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Compact Representation

• Illustration of a 4-input, 6 product term,
  3-output PLA
• 4x6x3
• All fuses shown intact (not yet programmed)
• This representation is closer to the wired
  logic physical implementation

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PLA Electrical Design
fuse detail
Wired Logic
fuse detail
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PLA Sharing Product Terms
F ABC AD AD G ABC ABC AD H ABC
BD J B AD
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Sharing Product Terms
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Example Programming a PLA

• Given
• F1 Sm(2, 4, 5, 7)
• F2 Sm(0, 1, 2, 4, 6)
• Use K-maps to minimize and look for common
  product terms
• Program functions into a simple PLA

minterm form
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K-Map Minimization

• Three-variable K-map for F1 Sm(2, 4, 5, 7)

F1
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K-Map Minimization

• Three-variable K-map for F2 Sm(0, 1, 2, 4, 6)

F2
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Programming the PLA
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Programming
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PLA Example 2

• Functions to implement are

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Minimum Product Terms

• Fewest are

Group both 1s and 0s to find fewest product terms
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PLA Programming Table

• Indicates intact fuse locations
• Helps to identify shared terms

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PLA For Example 2

• 3 inputs
• 4 product terms
• 2 outputs
• optional inversion of outputs

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Circuit For Example 2

• Note the inversion of the output to generate F1

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Before Programming

• Express functions in SOP form
• Try to reduce the number of product terms
• To use fewer of the rows
• Look at both 1s and 0s
• Number of literals in each term not as important
• Fewer may make circuit faster

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Create Programming Table

• What really gets generated is the programming
  table
• Chip programmed in special-purpose programming
  device
• uses personality modules for different devices

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PROM, PAL, PLA Assignment

• Sandige, Chapter 7
• 7 39
• 7 42
• 7 44
• 7 48
• Write out on paper photocopies from book
• Due on Wednesday, September 8, 2004 at start of
  class