Solutions For Design Verification

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• Test Program Generation Verification and
• Release Management

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Corporate Overview

• Founded in 1987
• Headquarters in Milpitas, CA
• Over 200 Customers Doing IC System Design
• Close Relationships With CAE ATE Vendors
• Offers full range of design-to-test and
  manufacturing productivity improvement solutions

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Partial Customers List

• LSI logic
• Motorola
• Schlumberger
• Infineon
• Silicon graphics
• Sun Microsystems
• Silicon magic
• Texas instruments
• Xilinx

• Advanced Micro Devices
• Agilent
• ATI
• Cisco Systems
• Credence Systems Corp
• Cypress Semiconductor
• Dallas Semiconductor
• Fujitsu Microelectronics
• Hewlett-Packard
• Hitachi

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Test Program Generation Verification
Challenges

• Shortening development and post-silicon debug
  time
• Verifying ATE test programs pre-silicon w/o
• tester
• Simulation pattern compatibility with the
  production tester
• Improving design-test communication

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Release Management Challenges

• Managing test program releases in multiple tester
  environment at many global sites for multiple
  family of devices
• Reducing paperwork and time to process program
  change requests
• Authorization, validation and tracking of test
  program changes
• Uniform methods of test program generation
• Automated Revision Control Procedures

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Simutest Solutions

• Test Program Generation Verification
• Verifier
• Fabless/IP companies Tester ready vectors
• TestWare
• Test Program Release Management
• Release Manager
• DFT/ATPG, Pay-per-use services
• Consulting Services

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Verifier Features

• Analyze to verify tester compatibilty
• Translator to create ATE test programs
• Playback to compare ATE test program and design
  test-bench
• Convert ATE test programs to VCD
• Support for most ATE
• All off-line and Pre-silicon

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Verifier Components

• Verifier
• Simulation log file reader/Test-bench Writer
• Tester format writer
• Tester format reader
• Verilog Playback
• Rule Analyzer/Tester Rule Checker
• Conditioners
• Waveform display (sim vs.tester)
• Compare
• Verilog driver, Java GUI, batch-mode scripts

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Analyze

• Identify tester compatibility issues early in
  design
• Reduce simulation iterations
• Tester ready vectors in fabless/IP environment
• Identify proper target tester to suite your
  simulation
• Comprehensive Analysis of simulation vectors
• Datasheet timing checks
• Tester resource compliance
• Test strategy compliance
• Provides detailed error messages to allow
  correction of simulation artifacts reports
  output Violation

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Translate

• Generate optimized test programs for target
  tester from simulation/ATPG log files
• Vector compression by repeats, loops and
  subroutines
• Extract timing from simulation or super-impose
  datasheet timings
• Process multiple simulation files to derive
  incremental timings
• Single-pass dynamic conditioners to remove
  simulation artifacts

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Translate
Log File
Pre Processor
Cyclization
Translator
SIF State
SIF Event
Definition File
Test Program
Simulation log file to ATE test program
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Playback

• Playback ATE Test program to Verilog using tester
  model. Let Verilog compare expected vs.
  re-simulated results
• Convert Test program into Verilog test bench
• Convert test program into VCD format

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Playback
Device Model
VCD
Verilog Simulator
Test Program
Verifier
Test bench
Test Bench
Compare
Compare
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Playback
Test Program
SIF
Playback
VCD
Compare
Waveform
Log file
Model
Simulation
Test Bench
Text Report
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Verilog Compare
Tick 0 info simulation invoked at Thursday jun
1st 16.27.49 2000
570 state changes on observable nets in 0.32
seconds. 1781 Events/second. Simulation stopped
at the end of time 60020.000ns.
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Static Compare
Inputs
Outputs
Original simulation file
Compare mismatch waveform display
Test program or re-simulated trace file
Compare
Compare mismatch text report
Compare spec file
- At-strobe, timing, cycle-cross-over, Compare
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Verifier Summary

• Innovative solutions
• Concurrent design and test program verification
• Pre-silicon and without tester
• Utilizes familiar and proven Verilog environment
• Improves design and test communication
• Reduces test cost
• Cost-effective, modular and expandable
  architecture
• Full functionality of pattern translation, Rule
  checking, displaying, editing and comparing

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Verifier Benefits

• Reduces the design-to-test transfer time
• Fewer design iteration
• Improves design test engineers communication
• Improves the quality of test
• Verifies the original design intent
• Increases first-pass silicon verification success
• Proven methodology

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Testware For fabless/IP Developer

• Transfer tester ready vectors to foundries
• Testware components
• Simulation log-file reader
• Built-in Cyclization
• Rule Analyzer
• Conditioners
• Verilog Playback
• Output in WGL, VCD formats

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Test Pattern Conversion Utilities
Source Tester
Target Tester
Test Program
Writer
Test Program
SIF Database
Reader
Tester To Tester
Target Simulator
Source Simulator


Stimulus-Response
Writer
Simulation File
SIF Database
Reader
Simulator To Simulator
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Simulators Testers Support

• Simulators
• VCD
• WGL
• STIL
• SCAN
• TDL
• ..
• Others

• Testers
• Credence
• Agilent
• LTX
• Nextest
• Teradyne
• Others

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Release Manager

• Integrated Framework
• Program Change Request
• Automated Customized Test Program Generator
• Revision Control System
• Commercial Database
• Authorize, validate, track program change
  requests at global sites electronically
• Maintain uniform Revision Control at global sites
  for multiple testers, devices, program types and
  process technology

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Release Manager Architecture
Database
E D I T O R S
Baseline
Test Fragments
Device
Valid ?
Change Request
Test Program Generator
Test Data Summary
Check out
Match ?
Revision Control
Yes
No
Compare
Compile/ Test
Datalog
Vesrsions
Binary Check in
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Release Manager Architecure
Test Programs/Reports/History/Versions
C-TPG
Validate
PCR
RCS
Oracle Database

• Product family
• Datasheet specs
• ProgramTemplates
• Program flow

• Tester info
• Site info
• Authorization
• Revisions

Create/Update/Retrieve/Request
Device/Test data

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Automated Test Program Generator
C-TPG
Test Program
Data
Flow
History
Oracle Database

• Product family
• Datasheet specs
• ProgramTemplates
• Program flow

• Tester info
• Site info
• Authorization
• Revisions

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Program Change Request (PCR)
Site
PCR
Valid?
Request
Report

• User
• Approval
• Product
• Program
• Release
• Site
• Changes
• Reason

Approval

• E-mail
• Print-outs

Oracle Database
Update

• Authorization
• Hierarchy
• History
• Specs
• Device Config

Is change valid?, Notify to approving
authority, Get approval, Record history
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Revision Control System
Test Programs
RCS
Versions

• Control releases for
• Multiple global sites
• Multiple testers
• Multiple device family
• Automated file transfers

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Revision Control System Menu
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Test Program Validator
Test Program Validator
Valid ?
Mis-matches
Oracle Database
AC/DC Parameters Tester timings/limits
Given a set of specs and tester timing
restrictions which it should meet, validate and
report all mis-matches in a test program
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Release Manager Summary

• Integrated set of tools for
• Automated Test Program generation
• Revision control
• Authorization, validation and tracking of changes
• Reusable methods for any tester
• Uniform procedures for global manufacturing sites

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Release Manager Benefits

• Significant productivity improvements over
  current methods
• Greater management visibility and control on
  process
• Improved inter-departmental communication
• Uniform procedures for multiple devices and
  multiple testers
• Reduce learning time and dependency on tester
  environment for routine tasks

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Consulting Services

• Test vector conversions
• Pay-per-use
• Process improvements for manufacturing test
  program generation/management
• DFT/ATPG services

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Visit us at Booth 1136