ECET 230 Course Marvelous Learning - snaptutorial.com

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ECET 230 Course Marvelous Learning -
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ECET 230 Course Marvelous Learning -
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ECET 230 Week 1 Homework For more classes
visit www.snaptutorial.com   1. Develop the
Boolean equation for the circuit shown below 2.
Determine the output Y in Problem 1 for the input
values shown below 3. Redraw the circuit in
Problem 1 using only 2-input NAND gates 4.Develop
the Boolean equation for the circuit shown below
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ECET 230 Course Marvelous Learning -
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ECET 230 Week 1 iLab Introduction to Quartus II,
VHDL, and the FPGA Board For more classes
visit www.snaptutorial.com   Objectives 1.Learn
How to write basic logic circuits using
VHDL. 2.Using Quartus II compile and simulate the
text file and then analyze the simulation for
proper operation. 3.Learn how to assign pins and
then how to download the program to the eSOC II
board. 4. Verify that the eSOC II board behaves
correctly when the output is what is expected
depending on the input configuration.
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ECET 230 Course Marvelous Learning -
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ECET 230 Week 2 Homework For more classes
visit www.snaptutorial.com   1. When a HIGH is on
the output of the decoding circuit below, what is
the binary code appearing on the inputs? 2. Write
the Boolean equations for each of the following
codes if an active-LOW decoder output is
required 3. Write the VHDL text file for a
3-to-8 decoder. 4. A 7-segment decoder/driver
drives the display below. Using the waveforms
shown, determine the sequence of digits that
appear on the display.
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ECET 230 Week 2 iLab Decoders and Multiplexers
For more classes visit www.snaptutorial.com   Obj
ectives Discover the operation of 7-segment
displays, BCD-to-7-semgment decoders,
multiplexers and demultiplexers. Demonstrate the
simulation of a discrete DEMUX and decode
operation with discrete components. Construct a
discrete circuit with these components. Use VHDL
to emulate this circuit within an FPGA.   Why
are the 330 ? resistors required for the discrete
logic circuit, but not for the MultiSim simulated
circuit or the eSOC III circuit?
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ECET 230 Week 3 Homework For more classes
visit www.snaptutorial.com   1.Determine the
decimal value of each of the following unsigned
binary numbers 2.Determine the decimal value of
each of the following signed binary number
displayed in the 2s complement form 3.
Determine the outputs (Cout, Sout) of a
full-adder for each of the following
inputs 4.The circuit below is an attempt to
build a half-adder. Will the Cout and Sout
function properly? Demonstrate your rationale.
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ECET 230 Course Marvelous Learning -
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ECET 230 Week 3 iLab Flip-Flops in VHDL For
more classes visit www.snaptutorial.com   Objectiv
es Simulate an edge-triggered D flip-flop.
Test a 74LS74 D flip-flop and compare against
predictions. Describe and simulate
edge-triggered D and J-K flip-flops with VHDL.
Test a 74LS112 J-K flip-flop and compare against
predictions. 1. Why is the condition when both
and are LOW considered illegal?   2. How does the
value you measured for tsetup compare with value
specified in the 74LS74 data sheet? You may need
to go on-line to find this value.  
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ECET 230 Week 4 Homework For more classes
visit www.snaptutorial.com   1. Sketch the Q
output for the waveforms shown below applied to
an active-LOW S-R latch. Assume that Q starts
LOW. 2. Sketch the Q output for the waveforms
shown. Assume that Q starts LOW. 3. Sketch the Q
output for the circuit shown below. Assume that Q
starts LOW. 4. Sketch the Q output for the
circuit shown below. Assume that Q starts LOW. 5.
Sketch the Q output for the circuit shown below.
Assume that Q starts LOW.
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ECET 230 Course Marvelous Learning -
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ECET 230 Week 4 iLab Introduction to Flip-Flops
For more classes visit www.snaptutorial.com   Obj
ectives Simulate an edge-triggered D flip-flop.
Test a 74LS74 D flip-flop and compare against
predictions. Describe and simulate
edge-triggered D and J-K flip-flops with VHDL.
Test a 74LS112 J-K flip-flop and compare against
predictions. 1. Why is the condition when both
and are LOW considered illegal?   2. How does the
value you measured for tsetup compare with value
specified in the 74LS74 data sheet? You may need
to go on-line to find this value.
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ECET 230 Course Marvelous Learning -
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ECET 230 Week 5 Homework For more classes
visit www.snaptutorial.com   1.Using Quartus II,
or an equivalent VHDL entry program, develop the
text file and simulation for the circuit below.
Attach the .vhd and simulation files. 2.What is
the output frequency of Q1 in the circuit shown
below? 3.A synchronous binary counter is used to
divide a 1 MHz input frequency to 3.90625 kHz.
What is the MOD number of the counter and how
many flip-flops are required?
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ECET 230 Course Marvelous Learning -
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ECET 230 Week 5 iLab Design of Synchronous
Counters For more classes visit www.snaptutorial
.com   Objectives 1.To understand the how to
design sequential counters using a VHDL logic
design file. 2.To design a basic synchronous up
binary counter using the VHDL Integer type. 3.To
be able to use IFTHENELSE statements in the
design of non-binary counters. 4.To design a Gray
code counter in a VHDL file and program the eSOC
II board.
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ECET 230 Course Marvelous Learning -
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ECET 230 Week 6 Homework For more classes
visit www.snaptutorial.com   1.The group of bits
10110101 is serially shifted (right-most bit
first) into an 8-bit shift register with an
initial state of 11100100. After two clock
pulses, the register contains (a) 01011110 (b)
10110101 (c) 01111001 (d) 00101101 2. With a 100
kHz clock frequency, eight bits can be serially
entered into a shift register in (a) 80 ms (b) 8
ms (c) 80 ms (d) 10 ms  
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ECET 230 Course Marvelous Learning -
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ECET 230 Week 6 iLab Design of a Simple State
Machine For more classes visit www.snaptutorial.
com   Objectives Deisgn a simple state
machine. In Figure 6.3, what is the purpose for
the arrows going from S1 to S0 and from S4 to S3?
Why are these needed? What are the advantages of
using state variables instead of a series of
IFTHENELSE statement? Give an example of a
finite state machine that can be easily
development using state diagrams and state
variables?
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ECET 230 Week 7 Homework For more classes
visit www.snaptutorial.com   1. Is the state
machine below a Moore machine or a Mealy machine?
Explain your rationale. 3. Using the state
diagram in Figure 10.44 on page 663 of the Dueck
textbook, briefly explain the operation of the
circuit shown. 4.Create the VHDL text file for
the state machine described in Problem 3. 5.
Create the Quartus II simulation for the state
machine shown in Problem 3.
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ECET 230 Course Marvelous Learning -
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ECET 230 Week 7 iLab Traffic Light Design
Program For more classes visit www.snaptutorial.
com   This lab will take a simple three light,
two-way intersection as in figure 1.0 and create
a working program for it. Based on the timing
chart 2.0, I will create a VHDL file and run a
simulation to achieve a basic formula for how the
intersection will work. Then using the eSOC
board, I will create a visual simulation with the
exception that I will be controlling the timing
of the light. ANSWERS TO QUESTIONS In Figure 6.3,
what is the purpose for the arrows going from S1
to S0 and from S4 to S3? Why are these needed?
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ECET 230 Course Marvelous Learning -
snaptutorial.com
The Best way to predict the Future is to create
it.....To Best way....
www.snaptutorial.com