4'3' Surface Effects Hot carrier injection Zener Walkout

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• 4.3. Surface Effects- Hot carrier injection-
  Zener Walkout
• Beta degradation due to Avalanche
• NBTI Negative Bias Temperature Instability
• - Parasitic surface channels and charge

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1. Hot carrier injection hot carriers in pinched
off region can generate e-h pairs by impact
ionization. Hot electrons can be injected into
oxide (increased Gate current), and holes stray
into substrate (back gate current).
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- Hot carrier injection hot carriers in pinched
off region can generate e-h pairs by impact
ionization. Hot electrons can be injected into
oxide (increased Gate current), and holes stray
into substrate (back gate current).
. Some of the hot electrons also desorbs the
Hydrogen-Si bonds at Si surface . gt This leads
to change in fixed-oxide charge, Qox and a
gradual shift of Vt.
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• Hot carrier injection The Preventive Measures

gt reduce E-field within pinchoff region, gt
reduce backgate doping in the immediate vicinity
of Drain, gt Deuterium-passivation rather than
H-passivation of Si dangling bonds at surface.
gt Long-channel devices have less effect due to
hot carriers (relatively).Note no injection
when MOSFET is under cutoff or linear mode
(Digital) injection under saturation mode
(analog circuits may have some MOSFETs under
continuously saturation mode.)
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• Hot carrier injection The Preventive Measures

gt reduce E-field within pinchoff region, gt
reduce backgate doping in the immediate vicinity
of Drain, gt Deuterium-passivation rather than
H-passivation of Si dangling bonds at surface.
gt Long-channel devices have less effect due to
hot carriers (relatively).Note no injection
when MOSFET is under cutoff or linear mode
(Digital) injection under saturation mode
(analog circuit as analog circuits have MOSFETs
under continuously saturation mode.)
? Prevention - LDD NMOS - Deuterium-passivation
instead of Hydrogen passivation - Some MOSFETs in
analog circuits operate in continuously saturated
condition as opposed to the Triode? Cuttoff
conditions in digital circuits. Therefore,
longer channel MOSFETs in analog circuits.
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2. Zener walkoutZener walkout slow increases
of Avalanche breakdown voltage during operation
of Zener diode and of EBJ of BJT (particularly
NPN). The EBJ Zener avalanche diode near
Si-oxide interface shows a several hundred mV
Zener walkout
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2. Zener walkoutZener walkout slow increases
of Avalanche breakdown voltage during operation
of Zener diode and of EBJ of BJT (particularly
NPN). The EBJ Zener avalanche diode near
Si-oxide interface shows a several hundred mV
Zener walkout
There are two models to explain this -
classical model Hot carrier injection and Qox
increase - new model role of Hydrogen
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2. Zener walkout, contd
Classical model Hot carrier injection and Qox
increase This classical model for explaining
this is --- the narrower depletion zone near the
Si surface has high E-field and thus easier
breakdown. Once breakdown occurs, hot carriers
are injected into oxide and fixed oxide charge,
Qox, increases which, in turn, increases the
depletion region near Si surface (this causes Vbr
to increase). Once the depletion near surface
is as wide as in the depletion down in the bulk,
the Vbr increase stops.
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2. Zener walkout, contd
New model Hydrogen compensation of Acceptors
This new model for explaining Zener walkout
focus on the role of hydrogen which isreleased
from Oxide-Si interface during breakdown ---
These H atoms migrate into p-type Si bulk (for
NMOS) and passivate the Acceptor impurities
(H-Acceptor bond), disabling the Acceptors to
produce holes, which, then, leades to wider
depletion region and thus increases Vbr (i.e.,
Zener walkout). The Zener walkout stops when
the supply of Hydrogen from Ox-Si interface is
exhausted. Zener walkback Gradual diffusion of
Hydrogen in p-Si reduces the H-compensation of
Acceptors therefore higher hole concentration
and narrower depletion region gt decreased
Vbr (Zener walkback). Refractory metal and its
silicide (Ti and TiSi) used in contact metal
getters (immobilizes) the Hydrogen atoms gt
reduces Hydrogen supply for Acceptor
compensation by Hydrogen gt reduced Zener walkout.
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2. Zener walkout, contd
? Prevention- Buried Zeners keep avalanche
region away from Si surface - Use field plates
(which stabilizes E-field in oxide)
Positive-biased field plate over p-Base of
NPN-EBJ Zener will deplete the p-Base near
surface and the Avalanche will happen deeper
(away from) Si surface. But it is ineffective.
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• 3. Avalanche-induced Beta degradation
• Avalanche breakdown of EBJ (particularly NPN)
  leads to lower BETA at the low Ic level.
• This is due to the increased Irec in the
  depletion region.
• 200-250C baking recovers BETA partially.
• Diffused Emitter BJT suffers this
• but Poly-emitter transistors suffer much more.

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• 3. Avalanche-induced Beta degradation
• Avalanche breakdown of EBJ (particularly NPN)
  leads to lower BETA at the low Ic level.
• This is due to the increased Irec in the
  depletion region.
• 200-250C baking recovers BETA partially.
• Diffused Emitter BJT suffers this
• but Poly-emitter transistors suffer much more.

CAUSE the desorbed Hydrogen leaves behind
dangling bonds at Si-oxide interface (diffused
Emitter) and in the Poly-mono Si boundary in
the Poly-emitter (grain boundary of
Poly-emitter). The dangling bonds act as
recombination centers and increase Irec.
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• 3. Avalanche-induced Beta degradation
• Avalanche breakdown of EBJ (particularly NPN)
  leads to lower BETA at the low Ic level.
• This is due to the increased Irec in the
  depletion region.
• 200-250C baking recovers BETA partially.
• Diffused Emitter BJT suffers this
• but Poly-emitter transistors suffer much more.

CAUSE the desorbed Hydrogen leaves behind
dangling bonds at Si-oxide interface (diffused
Emitter) and in the Poly-mono Si boundary in
the Poly-emitter (grain boundary of
Poly-emitter). The dangling bonds act as
recombination centers and increase Irec.
PREVENTION Operate BJT at lower than EBJ
voltage rating lt75VEBO for diffused-emitter
and lt50 VEBO for poly-emitter.
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• 4. Negative Bias Temperature Instability (NBTI)
• Vt magnitude increases gradually for Negative
  Gate bias (therefore PMOS).
• Higher Temperature accelerates the process.
  Thus, NBTI.
• 250C baking reverses NBTI partially.
• Positive Gate bias also produce PBTI maybe due
  to fixed charge at gate poly-oxide
  interface. (rarely causes trouble.)

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• 4. Negative Bias Temperature Instability (NBTI)
• Vt magnitude increases gradually for Negative
  Gate bias (therefore PMOS).
• Higher Temperature accelerates the process.
  Thus, NBTI.
• 250C baking reverses NBTI partially.
• Positive Gate bias also produce PBTI maybe due
  to fixed charge at gate poly-oxide
  interface. (rarely causes trouble.)

• CAUSE
• not fully understood.
• Positive oxide charge generated at oxide-Si
  interface perhaps by holes.
• NBTI occurs Only IF gate oxide is exposed to
  atmosphere (moisture) before gate poly is
  deposited.

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• 4. Negative Bias Temperature Instability (NBTI)
• Vt magnitude increases gradually for Negative
  Gate bias (therefore PMOS).
• Higher Temperature accelerates the process.
  Thus, NBTI.
• 250C baking reverses NBTI partially.
• Positive Gate bias also produce PBTI maybe due
  to fixed charge at gate poly-oxide
  interface. (rarely causes trouble.)

• CAUSE
• not fully understood.
• Positive oxide charge generated perhaps by holes
  at oxide-Si interface.
• NBTI occurs Only IF gate oxide is exposed to
  atmosphere (moisture) before gate poly is
  deposited.

• Prevention
• Not much can be done because gate oxide cant be
  un-exposed to atmosphere before poly-gate
  deposition.

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• 5. Parasitic Channels and Charge Spreading
• Metals on FOX can turn on channel if voltage is
  greater than Thick-Field Threshold.
• Parasitic PMOS if VGS more negative than
  Thick-field Threshold (Fig.4.10)
• Parasitic NMOS if VGS more positive than
  Thick-field Threshold. (Fig.4.10)

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• 5. Parasitic Channels and Charge Spreading
• Metals on FOX can turn on channel if voltage is
  greater than Thick-Field Threshold.
• Parasitic PMOS if VGS more negative than
  Thick-field Threshold (Fig.4.10)
• Parasitic NMOS if VGS more positive than
  Thick-field Threshold. (Fig.4.10)

• Charge Spreading Parasitic MOSFET can form even
  WITHOUT the Metal present on FOX. This is due
  to Static Charge present at interfaces between
  different layers above FOX. Fig.4.11

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5. Parasitic Channels and Charge Spreading,
Contd.

• CAUSE
• Parasitic PMOS forms
• gt Between any P-region (in Si) and Metal (on
  FOX) if VGS gt thick-field threshold
• gt Between any P-region (in Si) and enough
  negative charges (on oxide) if VGS gt
  thick-field threshold. Standard bipolar process
  is more vulnarable

• PREVENTION (CMOS and BiCMOS)
• Parasitic PMOS can be suppressed by field plate
  and/or channel stops. (Fig.4.14)

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5. Parasitic Channels and Charge Spreading,
Contd.

• PREVENTION (CMOS and BiCMOS)
• Parasitic PMOS can be suppressed by field plate
  and/or channel stops. (Fig.4.14)

Example of parasitic PMOS .
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5. Parasitic Channels and Charge Spreading,
Contd.

• PREVENTION (CMOS and BiCMOS)
• Parasitic PMOS can be suppressed by field plate
  and/or channel stops. (Fig.4.14)

Example of parasitic PMOS .
Consider HSR (shallow, light P-diffusion in
N-Tank)
Note pBase R has 200 Ohm/sq HSR has 1-10
kOhm/sq in Standard Bipolar
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5. Parasitic Channels and Charge Spreading,
Contd.

• PREVENTION (CMOS and BiCMOS)
• Parasitic PMOS can be suppressed by field plate
  and/or channel stops. (Fig.4.14)

Example of parasitic PMOS .
Consider HSR (shallow, light P-diffusion in
N-Tank)
Field plate a metal plate, biased to prevent
channel formation (connected to a
positive/negative electrode), provides
electrostatic shield, and thus prevent static
charge accumulation.
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5. Parasitic Channels and Charge Spreading,
Contd.

• PREVENTION (CMOS and BiCMOS)
• Parasitic PMOS can be suppressed by field plate
  and/or channel stops. (Fig.4.14)

• Poly leads running across N-well can form
  parasitic PMOS (Fig.4.17)

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5. Parasitic Channels and Charge Spreading,
Contd.

• PREVENTION (CMOS and BiCMOS)
• Parasitic PMOS can be suppressed by field plate
  and/or channel stops. (Fig.4.14)

• Poly leads running across N-well can form
  parasitic PMOS (Fig.4.17)

• Parasitic NMOS between two N-wells can be
  suppressed by surrounding the N-wells by PSD
  rings. The PSD ring (within the P-epi
  region) will have a Thick-field Threshold much
  higher than the P-epi areas. Thus the parasitic
  N-channels, even if it forms within the P-epi
  regions will be disconnected by these PSD-rings.
  (Fig.4.18)

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4. Parasiticscomponents - resistances -
capacitances between diffusions and
depositions main parasitic mechanisms -
substrate (injection) de-biasing - minority
carrier injection
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(1) Substrate Debiasing --- Model (Fig.4.20)
Standard Bipolar R1 a few 100s 1000s Ohms
R2 lt 10 Ohm CMOS, BiCMOS R1 small, ignored R2
Ac 600 kOhm/um2. Where Ac substrate
contact area
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(1) Substrate Debiasing --- Model (Fig.4.20)
Standard Bipolar R1 a few 100s 1000s Ohms
R2 lt 10 Ohm CMOS, BiCMOS R1 small, ignored R2
Ac 600 kOhm/um2. Where Ac substrate
contact area
Tolerance Limit for Minimum NPN Standard Bipolar,
Collector-Substrate Forward voltage Table 4.1
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Prevention Have Enough Substrate
Contacts!!! If substrate is HEAVILY doped,
Scribe Seal substrate contacts extract 5-10 mA.
If higher substrate currents are expected then
determine required contact area by Ac 10 r
tepi Is / Vd Ac required contact area in um2
Tepi epi thickness in um r epi resistivity
in Ohm-cm Is max substrate current in mA Vd
max allowable debiasing in V
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Prevention Have Enough Substrate
Contacts!!! If substrate is HEAVILY doped,
Scribe Seal substrate contacts extract 5-10 mA.
If higher substrate currents are expected then
determine required contact area by Ac 10 r
tepi Is / Vd Ac required contact area in um2
Tepi epi thickness in um r epi resistivity
in Ohm-cm Is max substrate current in mA Vd
max allowable debiasing in V
Example tepi 7 um, r 10 Ohm.cm, Is 20 mA,
Vd 0.3 V, then Ac 47,000 um2. If the scribe
seal contact is to conduct all Is, then for a
2mmx2mm tiny cheap, the contact width in scribe
seal 47,000um2 / (2mm x 4 sides x 1,000 um/mm)
about 5um.
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Prevention Have Enough Substrate
Contacts!!! If substrate is HEAVILY doped,
Scribe Seal substrate contacts extract 5-10 mA.
If higher substrate currents are expected then
determine required contact area by Ac 10 r
tepi Is / Vd Ac required contact area in um2
Tepi epi thickness in um r epi resistivity
in Ohm-cm Is max substrate current in mA Vd
max allowable debiasing in V
Example tepi 7 um, r 10 Ohm.cm, Is 20 mA,
Vd 0.3 V, then Ac 47,000 um2. If the scribe
seal contact is to conduct all Is, then for a
2mmx2mm tiny cheap, the contact width in scribe
seal 47,000um2 / (2mm x 4 sides x 1,000 um/mm)
about 5um.
lightly doped substrate (with heavy or light
doped isolation), or dielectrically isolated
substrates ? They follow different guidelines of
substrate contact.
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(2) Minority-Carrier Injection Any junction
(intended to be Reverse Biased) gets forward
biased (accidentally), then minority carriers
will be injected and produce unwanted
effect. Minority Injection EXAMPLES Standard
Bipolar process Electron injection into
substrate, and move into neighboring N-Tank.
Fig.4.21 ? If the Beta of parasitic Qp is 0.01
and 10 mA is injected into substrate, then the
tank will collect 100 uA! Enough to disrupt the
operation! CMOS NMOS-PMOS has lateral NPN
PNP parasitics which can feed each other.
Fig.4.22. Latchup. R1 (R of PMOS well) R2
(substrate R) usually prevent the self-feeding
between PNP NPN. ? IF BetaPBetaN gt 1, then
Latchup possibility! ? Prevention reduce the
Betas by Increasing the separation or by
increasing the Base-region doping of the
Parasitic BJTs. Prevention of Substrate
Injection Insert Minority-collecting GUARD
RING! Examples Electron collecting guard-ring
Fig.4.23, Fig.4.24, Fig.4.25 Hole Guard Rings
Fig.4.26, Fig.4.27 P-bar (pBase strip) and N-bar
(deep N strip) to stop cross injection
Fig.4.28, Fig.4.29 -- P-bar collects minority
holes, and N-bar repels minority holes.