Digital Testing: Sequential Circuits

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Digital Testing Sequential Circuits

• Samiha Mourad
• Santa Clara University

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Outline

• Issues in testing sequential circuits
• Types of Tests
• Functional
• Deterministic
• Checking experiment
• Iterative array

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Importance of Sequential Circuits

• Most circuits are sequential
• The outputs depends on the input and
  the internal states
• Must drive the circuit first in a know state
  prior to applying the patterns that sensitize
  the faults to the outputs
• Use global reset or
• a synchronizing sequence
• Timing is an important factor
• Static and essential hazard

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Types of Tests

• Exhaustive 2is McCluskey 1981
• Pseudorandom Wunderlich 1989
• Not effective because it is not sufficient to
  apply the patterns, they should be done in the
  appropriate sequence
• Checking experiment
• Fault oriented, adaptation of combinational
  test
• Check literature for more recent algorithms

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Checking Experiment

• Synchronizing sequence SS place the FSM in a
  known state
• Homing sequence HS places the FSM in a known
  state that is identifiable by the output
  sequence
• Distinguishing sequence DS produces an
  output sequence that defines uniquely the
  initial state at which the sequence was applied
• Transition sequence TS indicates the
  transition form one state to any other

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Example

• Table 6.9 State Table for a Mealy FSM M
• Present Next State
• State I0 I1
• A C,1 B,0
• B C,0 B,1
• C D,1 C,1
• D A,1 C,0

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Transition Sequence

• Start form any state

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Distinguishing Sequence

• Start from the uncertainty all the states
• and form successor trees until an homogenous or
  a trivial uncertainty is reached

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Table 6.10

• (a) Homing Sequences (b) Applying
  Distinguishing Sequences 10
• HS Final S Output
• 0 C 0 Initial Final Out
• 00 D 01 State State seq
• 01 B 01 A C 00
• C 11 B C 10
• 10 C 00 C D 11
• D 01 D D 01

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Synchronizing Sequence
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Checking Experiment

• 1. Initialize M using an SS or HS to state S0
• 2. Apply a DS to verify this state
• 3. Let the final state obtained in the preceding
  step be Si
• 4. Apply a DS to verify Si
• 5. Repeat steps 3 and 4 until all states have
  been identified
• 6. If in this process, a state Sj is not
  reachable, apply a TS to get you to this state
  and apply a DS to verify it
• 7. Use the TS to verify all transitions except
  for those already verified in step 5

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The Checking Sequence part 1

• Time 0 1 2 3 4 5 6
• Input 0 1 0 1 0 0 1
• State ABCD C C D C D A
• Output -- 0 1 1 0 1 1

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The Checking Sequence part 2

• 7 8 9 10 11 12 13 14 15
• 0 0 0 1 1 0 1 0 1
• B C D A B B C C D
• 0 0 1 1 0 1 0 1 1

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The Checking Sequence part 3

• 16 17 18 19 20 21 22 23 24
• 0 0 0 1 1 1 0
• C D A B A B B C
• 0 1 1

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Historical Perspective

• 1962 Seshu First heuristic technique
• 1964 Hennie Checking experiment
• 1964 Carter Scan IBM for system/360
• 1966 Roth Dalgorithm
• 1967 Kohavi Fault tolerant FSM
• 1968 Kubo Second heuristic technique
• 1973 Williams Scan Design (Stanford)
• 1984 Putzolu Third heuristic ITG (IBM)
• 1986 Agrawal Partial scan
• 1987 Xilinx FPGA
• 1988 Marlett RISP
• 1989 Gheewala Crosscheck
• Later Check literature

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Iterative Logic Arrays

• 1. Cut the fewer number of the feedback wires to
  make the circuit acyclic (combinational)
• 2. Each feedback wire is an a pseudo input (PI)
  and a pseudo output (PO)
• 3. Consider different time frames decided by the
  clock
• or / and the inputs values
• 4. Use D-algorithm or any other to detect the
  faults
• 5. Start with the final frame at which the fault
  is observed and trace backward to an earlier
  frame until
• the signal are justified
• 6. The PI cannot be assigned any values x? I ?
• 7. Repeat 5 until all signal are justified, if
  there is a conflict, an inconsistency, trackback
  and select another justification path

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Sequential Circuit Model
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An Example
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Time Frames
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Another Example
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Time Frames Example 2