Electronics Bridging Course

1
Lecture 2

• Electronics Bridging Course
• Fall Semester 2003

2
Outline

• Review of three representations for combinational
  logic
• truth tables,
• graphical (logic gates), and
• algebraic equations
• Relationship among the three
• Adder example
• Formal description of Boolean algebra
• Laws of Boolean algebra

3
Combinational Logic (CL) Defined

• yi fi(x0 , . . . . , xn-1), where x, y are
  0,1.
• Y is a function of only X.
• If we change X, Y will change immediately (well
  almost!).
• There is an implementation dependent delay from X
  to Y.

4
CL Block Example 1

• Boolean Equation
• y0 (x0 AND not(x1))
• OR (not(x0) AND x1)
• y0 x0x1' x0'x1
• Gate Representation

• Truth Table Description

How would we prove that all three representations
are equivalent?
5
Boolean Algebra/Logic Circuits

• Why are they called logic circuits?
• The 19th Century Mathematician, George Boole,
  developed a math. system (algebra) involving
  formal principles of reasoning, Boolean Algebra.
• His variables took on TRUE, FALSE
• Later Claude Shannon (father of information
  theory) showed (in his Masters thesis!) how to
  map Boolean Algebra to digital circuits
• Primitive functions of Boolean Algebra

6
Relationship Among Representations

• Theorem Any Boolean function that can be
  expressed as a truth table can be written as an
  expression in Boolean Algebra using AND, OR, NOT.

How do we convert from one to the other?
7
Notes on Example 1

• The example is the standard function called
  exclusive-or (XOR,EXOR)
• Has a standard algebraic symbol
• And a standard gate symbol

8
CL Block Example 2

• 4-bit adder
• R A B,
• c is carry out

• Truth Table Representation

In general 2n rows for n inputs. Is there a
more efficient (compact) way to specify this
function?
256 rows!
9
4-bit Adder Example

• Motivate the adder circuit design by hand
  addition
• Add a0 and b0 as follows

• Add a1 and b1 as follows

r a XOR b c a AND b ab
r a XOR b XOR ci co ab aci bci
10
4-bit Adder Example

• In general
• ri ai XOR bi XOR cin
• cout aicin aibi bicin cin(ai bi) aibi
• Now, the 4-bit adder

Full adder cell
ripple adder
11
4-bit Adder Example

• Graphical Representation of FA-cell
• ri ai XOR bi XOR cin
• cout aicin aibi bicin

• Alternative Implementation
• ri (ai XOR bi) XOR cin
• cout cin(ai bi) aibi

12
Boolean Algebra

• Defined as

13
Logic Functions

• Do the axioms hold?
• Ex communitive law 01 10?

14
Other logic functions of 2 variables (x,y)
Look at NOR and NAND

• Theorem Any Boolean function that can be
  expressed as a truth table can be expressed using
  NAND and NOR.
• Proof sketch
• How would you show that NAND or NOR is sufficient?

15
Laws of Boolean Algebra

• Duality A dual of a Boolean expression is
  derived by interchanging OR and AND operations,
  and 0s and 1s (literals are left unchanged).

Any law that is true for an expression is also
true for its dual. Operations with 0 and 1 1.
x 0 x x 1 x 2. x 1 1 x 0
0 Idempotent Law 3. x x x x x
x Involution Law 4. (x) x Laws of
Complementarity 5. x x 1 x x
0 Commutative Law 6. x y y x x y y x
16
Laws of Boolean Algebra (cont.)

• Associative Laws
• (x y) z x (y z) x y z x (y z)
• Distributive Laws
• x (y z) (x y) (x z) x (y z)
• (x y)(x z)
• Simplification Theorems
• x y x y x (x y) (x y) x
• x x y x x (x y) x
• (x y) y x y (x y) y x y
• DeMorgans Law
• (x y z ) (x y z )
• x y z x y z
• Theorems for Multiplying and Factoring
• (x y) (x z) x y x z
• x z x y (x z) (x y)
• Consensus Theorem
• x y y z x z (x y) (y z)
  (x z)
• x y x z (x y) (x z)

17
Proving Theorems via axioms of Boolean Algebra

• Ex prove the theorem x y x y x
• x y x y x (y y) distributive law
• x (y y) x (1) complementary law
• x (1) x identity
• Ex prove the theorem x x y x
• x x y x 1 x y identity
• x 1 x y x (1 y) distributive law
• x (1 y) x (1) identity
• x (1) x identity

18
DeMorgans Law
(x y) x y
(x y) x y

• DeMorgans Law can be used to convert AND/OR
  expressions to OR/AND expressions
• Example z abc abc abc abc
• z

19
Algebraic Simplification

• Ex full adder (FA) carry out function
• Cout abc abc abc abc

20
Algebraic Simplification

• Ex full adder (FA) carry out function
• Cout abc abc abc abc
• abc abc abc abc abc
• abc abc abc abc abc
• (a a)bc abc abc abc
• (1)bc abc abc abc
• bc abc abc abc abc
• bc abc abc abc abc
• bc a(b b)c abc abc
• bc a(1)c abc abc
• bc ac ab(c c)
• bc ac ab(1)
• bc ac ab

21
Outline

• Canonical Forms
• They give us a method to go from TT to Boolean
  Equations
• Two-level Logic Simplification
• K-map method
• Multi-level Logic
• NAND/NOR networks
• EXOR revisited

22
Canonical Forms

• Standard form for a Boolean expression - unique
  algebraic expression from a TT.
• Two Types
• Sum of Products (SOP)
• Product of Sums (POS)

• Sum of Products (disjunctive normal form, minterm
  expansion). Example
• minterms a b c f f
• abc 0 0 0 0 1
• abc 0 0 1 0 1
• abc 0 1 0 0 1
• abc 0 1 1 1 0
• abc 1 0 0 1 0
• abc 1 0 1 1 0
• abc 1 1 0 1 0
• abc 1 1 1 1 0

One product (and) term for each 1 in f f abc
abc abc abc abc f abc abc
abc
23
Sum of Products (cont.)

• Canonical Forms are usually not minimal
• Our Example
• f abc abc abc abc abc
• abc ab ab
• abc a (xy x y x)
• a bc
• f abc abc abc
• ab abc
• a ( b bc )
• a ( b c )
• ab ac

24
Canonical Forms

• Product of Sums (conjunctive normal form, maxterm
  expansion). Example
• maxterms a b c f f
• abc 0 0 0 0 1
• abc 0 0 1 0 1
• abc 0 1 0 0 1
• abc 0 1 1 1 0
• abc 1 0 0 1 0
• abc 1 0 1 1 0
• abc 1 1 0 1 0
• abc 1 1 1 1 0
• One sum (or) term for each 0 in f
• f (abc)(abc)(abc)
• f (abc)(abc)(abc)(abc)(abc)
• Mapping from SOP to POS (or POS to SOP) Derive
  TT then proceed.

25
Two-level Logic Simplication

• Key tool The Uniting Theorem
• x (y y) x (1) x
• a b f f ab ab a(bb) a
• 0 0 0 b values change within
• 0 1 0 the on-set rows
• 1 0 1 a values dont change
• 1 1 1 b is eliminated, a remains
• a b g g abab (aa)b b
• 0 0 1 b values stay the same
• 0 1 0 a values changes
• 1 0 1
• 1 1 0 b remains, a eliminated

26
Boolean Cubes

• Visual technique for identifying when the Uniting
  Theorem can be applied

• Sub-cubes of on nodes can be used for
  simplification.
• On-set - filled in nodes, off-set - empty nodes

27
3-variable cube example

• FA carry out
• a b c cout
• 0 0 0 0
• 0 0 1 0
• 0 1 0 0
• 0 1 1 1
• 1 0 0 0
• 1 0 1 1
• 1 1 0 1
• 1 1 1 1

What about larger sub-cubes?

• abc abc abc abc
• ac ac ab a ab a
• Both b c change, a is asserted remains
  constant.

28
Karnaugh Map Method

• K-map is an alternative method of representing
  the TT and to help visual the adjacencies.

29
Karnaugh Map Method

• Examples

1. Circle the largest groups possible. 2. Group
dimensions must be a power of 2.
30
K-maps (cont.)
Circling Zeros
31
BCD incrementer example
a b c d w x y z 0 0 0 0 0 0 0 1 0 0 0 1 0 0
1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0
0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1
1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1
0 1 0 - - - - 1 0 1 1 - - - - 1 1 0 0
- - - - 1 1 0 1 - - - - 1 1 1 0 - - -
- 1 1 1 1 - - - -
w x y z
32
Higher Dimensional K-maps
33
Multi-level Combinational Logic

• Example reduced sum-of-products form
• x adf aef bdf bef cdf cef g
• implementation in 2-levels with gates
• cost 7-input OR, 6 3-input AND
• 50 transistors 25 wires
• (19 literal plus 6 internal)
• delay 3-input AND gate delay 7-input OR
  gate delay
• Factored form
• x (a b c)(d e)f g
• cost 1 3-input OR, 2 2-input OR, 1 3-input AND
• 20 transistors
• delay 3-input OR 3-input AND 2-input OR
• Which is faster?
• In general Using multiple levels (more than 2)
  will reduce the cost. Sometimes also delay.
  Sometime a tradeoff between cost and delay.

34
Multi-level Combinational Logic

• Example F abc abd acd bcd
• let x ab y cd
• f xy xy
• No convenient hand methods for multi-level logic
  simplification
• CAD Tools, example misII (UCB)
• exploit some special structure, example adder
• Are these optimizations still relevant for LUT
  implementations?

35
NAND-NAND NOR-NOR Networks

• DeMorgans Law
• (a b) a b (a b) a b
• b b (a b) (a b) (a b)
• push bubbles or introduce in pairs or remove
  pairs.

36
NAND-NAND NOR-NOR Networks

• Mapping from AND/OR to NAND/NAND

37
NAND-NAND NOR-NOR Networks

• Mapping AND/OR to NOR/NOR
• OR/AND to NAND/NAND

• Mapping OR/AND to NOR/NOR

38
Multi-level Networks

• F a(b cd) bc
• Convert to NANDs (note fanout)

39
EXOR Function

• Parity, addition mod 2
• x xor y xy xy
• x y xor xnor
• 0 0 0 1
• 0 1 1 0
• 1 0 1 0
• 1 1 0 1
• Another approach