ECE 353 Introduction to Microprocessor Systems

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ECE 353Introduction to Microprocessor Systems
Week 9

• Michael G. Morrow, P.E.

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Topics

• Memory technologies
• Organization and operation of typical SRAM, EPROM
  and flash memory devices
• Memory subsystem design
• Address decoder implementation
• SRAM timing characteristics

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Memory Terminology

• How could we classify memory devices?
• Read-Only Memory (ROM)
• In common usage, ROM is memory that is
  nonvolatile.
• Random-Access Memory (RAM)
• The time required to access any memory location
  is the same i.e. it does not need to be
  accessed in a specific order.
• In common usage, RAM is memory that can be read
  or written with equal ease.

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Memory Technologies

• ROM (non-volatile)
• Masked ROM
• Field programmable
• EPROM
• OTP PROM (fuse or EPROM)
• Electrically erasable
• EEPROM (or E2PROM)
• Flash memory
• RAM (volatile)
• SRAM
• DRAM
• Pseudo-SRAM
• Emerging memory technologies

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Memory Organization

• Logical organization
• Organization as seen looking at the device from
  the outside
• Linear array of registers (memory locations)
• Width number of bits in each memory location
• Depth number of memory locations
• Usually written as depth x width (i.e. 32k x 8)
• Physical organization
• Different physical organizations can be used to
  implement the same logical organization
• Physical organization affects performance and cost

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SRAM Interfaces

• RAM with 3 control inputs
• /CS, /OE, /WE
• Read
• Write
• aka Intel style
• RAM with 2 control inputs
• E (CS), R/W (or /WE)
• aka Motorola style

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SRAM Organization

• Logical Organization
• Typically 1, 4 , 8 or 16 bit widths
• Physical Organization
• Rectangular bit array
• Two-level decoding (row and column)
• Characteristic delays and timing requirements are
  specified in memory devices datasheet (Example)
• NV-SRAM
• Uses an alternate power source to maintain SRAM
  when system power is off
• Requires logic to switch power sources and
  prevent spurious writes during power-up/power-down

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EPROM

• Electrically programmable, non-volatile
• Requires UV light to erase
• Quartz window in package
• Floating polysilicon gate avalanche injection MOS
  transistor (FAMOS)
• Operation
• Programmer loads device out-of-circuit
• OTP EPROMs eliminate quartz window
• EEPROMs are electrically erasable
• Byte-erasable / writeable
• Low-density
• JEDEC Packages

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Flash Memory

• Actually Flash EEPROM, commonly just called flash
  memory
• Characteristics
• Technologies
• Endurance
• Blocking, programming and erasing
• Applications
• ROM replacement
• GP NV-RAM
• Solid-state disk (flash-disk) Example

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Memory Subsystem Design

• Memory banks
• Increasing memory width
• Increasing memory depth
• Increasing memory width and depth
• Address decoding
• Exhaustive (full) vs. partial (reduced) decoding
• Boundaries
• If address is a 2n boundary, then what is the
  result of (address AND (2n-1))?
• We normally decode memory devices to be aligned
  on boundaries at least as large as they are

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Memory Architectures

• Wide (n-byte) buses
• Addressing effects
• Byte transfer support
• Data lanes
• Control signals
• Bus resizing
• Static
• Configurable
• Dynamic

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Memory Subsystems Review

• What is the purpose of an address decoder
  circuit, and where does its output usually get
  connected?
• What is exhaustive decoding, and what effects
  does it have?
• What is partial decoding, and what effects does
  it have?

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SRAM Timing Characteristics

• An SRAM device has key timing parameters
  specified for the read cycle.
• tAA address access time
• tRDHA data valid after address changes
• tACS chip select access time
• tRHCS data valid after chip select
• tCHZ time until device floats bus
• tOE output enable access time
• tOHZ time until device floats bus
• tRC read cycle time
• The write cycle has a complementary set of
  specifications.

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7C1046SRAM
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27C512EPROM
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HM624100HCSRAM
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SRAM Timing Compatibility

• In order to ensure that we will be able to
  reliably read and write the memory device, we
  need to ensure that the processor system bus
  interface is compatible with the memory device.
• This is accomplished by analyzing the timing for
  all relevant parameters of both the processor and
  memory, and ensuring that the operations can be
  completed reliably.

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Wrapping Up

• Quiz 2 will be held Thursday 11/5/2007 at
  715-830pm in 1106ME
• Covers educational objectives for modules 3 and 4
  (weeks 5 through 8)
• Single 3x5 card with original handwritten notes
• No calculators
• Instruction set references and any needed
  datasheets will be provided
• Reading for next week
• Supplement 3, review chapter 9 in text

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JEDEC Standard Packages
http//www.jedec.org/download/search/3_07_05R12.pd
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Flash Blocks
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Flash Memory ApplicationDisk-on-Key

• Up to 64GB nonvolatile storage
• And climbing
• No battery or power supply

Specifications Data retention up to 10 years
Erase cycles 1,000,000 times Shock resistance
1000 G (maximum)
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RAM Read 3 control signals
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RAM Write 3 control signals
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Increasing Memory Depth
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Increasing Memory Width
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Increasing Memory Depth Width