CSCE 612: VLSI System Design

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CSCE 612 VLSI System Design

• Instructor Jason D. Bakos

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MOSFET Theory
p-type body majority carriers are holes
accumulation mode
Vt depends on doping and tox
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Regions of Operation
Gate to channel Vgs near source Vgd near drain

• Switching delay is determined by
• time required to charge/discharge gate
• time for current to travel across channel

drain
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Ideal I-V Characteristics
Linear region
(charge)
(carrier velocity, m is mobility)
(electric field)
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Ideal I-V Characteristics
Saturation region
into equation
nmos
cutoff
linear
saturation
Holes have less mobility than electrons, so
pmoss provide less current (and are slower) than
nmoss of the same size
pmos
Which parameters do we change to make MOSFETs
faster?
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Nonideal I-V Effects

• Velocity saturation and mobility degradation
• Lower Ids than expected
• At high lateral field strength (Vds/L), carrier
  velocity stops increasing linearly with field
  strength
• At high vertical field strength (Vgs / tox) the
  carriers scatter more often
• Channel length modulation
• Saturation current increases with higher Vds
• Subthreshold conduction
• Current drops exponentially when Vgs drops below
  Vt (not zero)
• Body effect
• Vt affected by source voltage relative to body
  voltage
• Junction leakage
• S/D leaks current into substrate/well
• Tunneling
• Gate current due to thin gate oxides
• Temperature dependence
• Mobility and threshold voltage decrease with
  rising temperature

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C-V Characteristics

• Capacitors are bad
• Slow down circuit (need to use more power),
  creates crosstalk (noise)
• Gate is a good capacitor
• Gate is one plate, channel is the other
• Needed for operation attracts charge to invert
  channel
• Source/drain are also capacitors to body (p-n
  junction)
• Parasitic capacitance
• Diffusion capacitance
• Depends on diffusion area, perimeter, depth,
  doping levels, and voltage
• Make as small as possible (also reduces
  resistance)

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Gate Capacitance

• Gates capacitance
• Relative to source terminal
• CgsCOXWL
• Assuming minimum length
• CgsCpermW
• Cperm COXL (eOX/tOX)L
• Fab processes reduce length and oxide thickness
  simultaneously
• Keeps Cperm relatively constant
• 1.5 2 fF / um of width

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Gate Capacitance
Five components Intrinsic Cgb, Cgs,
Cgd Overlap Cgs(overlap), Cgd(overlap) C0
WLCox
Parameter Cutoff Linear Saturation
Cgb C0 0 0
Cgs 0 C0/2 2/3 C0
Cgd 0 C0/2 0
Sum C0 C0 2/3 C0
CgsolCgdol0.2-0.4 fF / um of width
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Parasitic Capacitance

• Source and drain capacitance
• From reverse-biased PN junction (diffusion to
  body)
• Csb, Cdb
• Depends of area and perimeter of diffusion,
  depth, doping level, voltage
• Diffusion has high capacitance and resistance
• Made small as possible in layout
• Approximately same as gate capacitance (1.5 2
  fF / um of gate width)

Isolated, shared, and merged diffusion regions
for transistors in series
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Switch-Level RC Delay Models
Delay can be estimated as R 6C FET passing
weak value has twice the resistance