A Parallel Path Receiver Architecture

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A Parallel Path Receiver Architecture for 60 GHz
CMOS Radio Systems
January 25, 2002 Cheol-Woong Lee Professor Paul
R. Gray
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60 GHz CMOS Radio Systems
5 GHz of available bandwidth (59 GHz64 GHz) For
high performance, we need very high speed and
high resolution ADC such as 1.2 GS/s 10 bit
ADC. The digital implementations of the physical
and link layer functions have to be clocked at
rates substantially above 1 GHz, which obviously
doesnt bode well for power dissipation and
complexity.
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60 GHz CMOS Radio Systems
4QAM 8 bits 16QAM 81 bits 64QAM 82 bits
The resolution requirement for ADC is constant,
regardless of a signal bandwidth in the given
modulation scheme.
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Talk Guideline
Study on ADC Performance Limit Parallelism and
OFDM Parallel Path Receiver Architecture Circuit
Building Blocks Implementation Issues
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ADC Performance Limit
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Voltage Error due to Jitter
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Voltage Error of Sine Wave
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SNR due to Jitter
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Voltage Error of Band-limited Signal
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SNR due to Jitter of Band-limited Signal
Example
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Aperture Jitter Spectrum
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(No Transcript)
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8bit 1.2 GS/s ADC
10bit 300MS/s ADC
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8bit 1.2 GS/s ADC
10bit 300MS/s ADC
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8bit 1.2 GS/s ADC
10bit 300MS/s ADC
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8bit 1.2 GS/s ADC
10bit 300MS/s ADC
Parallelism !
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Parallelism
10bit 1.2 GS/s ADC
10bit 300MS/s ADC
10bit 300 MS/s ADC
Lets discuss how we can make it work.
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Talk Guideline
Study on ADC Performance Limit Parallelism and
OFDM Parallel Path Receiver Architecture Circuit
Building Blocks Implementation Issues
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There is isolation between Communication Systems
and Circuit Designs.
Communication Specification
Layer 1
Layer 2
Circuit designers try to meet the specification.
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Understanding both communication application and
circuit limitation may produce
a better solution.
A relaxed circuit requirement based on a new
communication architecture.
A new communication architecture based on circuit
limitation.
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60 GHz CMOS Radio Systems
Establishing a 1 Gbit link means that the digital
implementations of the physical and link layer
functions have to be clocked at rates
substantially above 1 GHz, which obviously
doesnt bode well for power dissipation and
complexity. Rather than establishing the link as
a single serial high rate channel, the same can
be accomplished by combining multiple parallel
lower rate channels. Source Prof. Brodersen
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60 GHz CMOS Radio Systems
The advantage of parallelism is that the
requirements on the baseband and link layer
electronics are substantially reduced and that
power dissipation is lowered through the use of
extensive concurrency. Interesting questions
remain in the design of the link layer (how to
parallelize the data over a number of channels
with time-varying characteristics) and the
baseband processor (how to simultaneously process
multiple channels.) Source Prof. Brodersen
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Parallelized Channel
Wideband Channel
Parallelized Channel
IF
IF
BB
BB
BB
BB
BB
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Parallelism and OFDM
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Guard Band and Inner Null Band
Wideband Channel
GB
Parallelized Channel
Inner Null Band
GB
GB GB Inner Null Bands
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Cyclic Prefix
In order to combat the multi-path, Cyclic prefix
should be inserted. The length of Cyclic prefix
is determined by the multi-path, not by the
receiver architecture. Parallelized Channel has
the same length of Cyclic Prefix with the
original channel.
Wideband Channel
Parallelized Channel
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Talk Guideline
Study on ADC Performance Limit Parallelism and
OFDM Parallel Path Receiver Architecture Circuit
Building Blocks Implementation Issues
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Comparison
Path Mismatch, Complicated digital
calibration Sensitive to Sampling Jitter Baseband
Filter Design is hard. High Clock Frequency to
Digital System
No Path Mismatch, No digital calibration Less
Sensitive to Jitter Baseband Filter Design is
easy. Slow Clock Frequency to Parallel Digital
System
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20 GHz Radio System
22.4625 GHz
22.7825 GHz
RF
300 MHz
320 MHz
2.35
2.425
2.5
2.575 GHz
IF
BB
75 MHz
75 MHz
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Parallel Path Receiver Architecture
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Talk Guideline
Study on ADC Performance Limit Parallelism and
OFDM Parallel Path Receiver Architecture Circuit
Building Blocks Implementation Issues
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Main PLL for 20 GHz Radio System
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Multiple Frequency Synthesizer
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Multiple Frequency Synthesizer
70 Power!
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Multiple Frequency Synthesizer
2.575 GHz
2.425
150 MHz
0
150 MHz
0
Single Side Band Mixing
Frequency Detection Mixing
Loop Filtering
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Multiple Frequency Synthesizer
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Problem in Active Mixers
IF
IF
Regardless of Signal Bandwidth, the power
dissipation for the mixers is the same. This
means Parallel Architecture requires (N-1) times
more power for the mixers
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IF Amplifier Passive Mixers
Passive Mixers dont consume power and IF
Amplifier can be shared with passive mixers in
order to achieve enough conversion gain.
Clock Feed Through from other clock paths is not
a problem.
2.35
2.425
2.5
2.575 GHz
IF
0
75
150
225 MHz
BB
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Talk Guideline
Study on ADC Performance Limit Parallelism and
OFDM Parallel Path Receiver Architecture Circuit
Building Blocks Implementation Issues
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Cheol says, Complexity is Simple, Simplicity is
Complex.
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Cheol says, Complexity is Simple, Simplicity is
Complex.
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Complexity can be Simple.
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Looks Complex, but
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Looks Complex, but Parallelism relaxes design
requirements.
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Looks Complex, but Parallelism relaxes design
requirements. In reality, it is just the
collection of simple building blocks.
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Looks Complex, but Parallelism relaxes design
requirements. In reality, it is just the
collection of simple building blocks. I will
design building blocks simultaneously and
consider the relationship between the building
blocks.
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Looks Complex, but Parallelism relaxes design
requirements. In reality, it is just the
collection of simple building blocks. I will
design building blocks simultaneously and
consider the relationship between the building
blocks. Complexity can be simple.