Design Vision

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Design Vision
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Cell-Based Design Flow
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Design Vision

• The Design Vision tool is the graphical user
  interface (GUI) to the Synopsys synthesis
  environment.
• Design Vision provides menu commands and dialog
  boxes for the most commonly used synthesis
  features. In addition, you can enter any dc_shell
  command on the command line in the GUI or the
  shell.

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.sypnopsys_dc.setup file
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Logic Syntheis Overview(1/3)
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Logic Syntheis Overview(2/3)
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Logic Syntheis Overview(3/3)

• RTL is elaborated and analyzed then RTL is mapped
  to some form of internal representative library
  (Synopsys uses GTECH as reference to internal
  library).
• During optimization phase, GTECH cells are mapped
  to actual technology library based on
  constraints.
• Output of Synthesis tool is gate-level netlist,
  which is a completely structural description with
  only standard cells at the leaves of the design,
  along with various area and timing reports.

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Logic Synthesis
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Design object
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Static Timing Analysis
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Setup Hold Time Check
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Nonblocking v.s blocking

• Blocking nonblocking coding guideline
• Dont mix blocking non blocking statement in a
  same block
• nonblocking statement that is used to declare a
  sequential element
• blocking statement that is used to declare a
  combinational circuit

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Synthesizable Verilog HDL

• Non-Blocking and Blocking
• Use non-blocking assignments within
  sequential always block

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Synthesizable Verilog HDL

• Use blocking assignments within combinational
  always block.

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Synthesizable Verilog HDL

• Use non-blocking assignments within sequential
  always block

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Synthesizable Verilog HDL

• Use blocking assignments within combinational
  always block

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Always block statement

• Can be a blocking or nonblocking statement
• Dont declare a same value assignment more than 1
  always block

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Latch Inference

• A variable assigned within an always block that
  is not fully specified

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if Statement

• Whats the difference between these two coding
  styles?

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synthesis parallel_case

• Parallel version, assuming we can guarantee only
  one 1 in the input

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synthesis parallel_case

• Parallel version of priority encoder
• Note parallel case directive is not used,
  synthesis adds appropriate matching logic to
  force priority

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translate_off and translate_on Directives

• Use these directives when your Verilog source
  code contains commands specific to simulation
• // synopsys translate_off
• / synopsys translate_off /
• // synopsys translate_on
• / synopsys translate_on /

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????
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Case Statement

• If a case statement is not a full case, it will
  infer a latch

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Case Statement

• If you do not specify all possible branches, but
  you know the other branches will never occur, you
  can use //synopsys full_case directive to
  specify full case

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Combinational Always Block

• Sensitivity list must be specified completely,
  otherwise synthesis may mismatch with simulation

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Wire Register

• Reg A variable in Verilog
• Use of reg data type is not exactly synthesized
  to a really register
• Use of wire reg
• When use wire ? usually use assign and
  assign does not appear in always block
• When use reg ? only use ab , always appear
  in always block

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Register Inference

• A register (flip-flop) is implied when you use
  the _at_(posedge clk) or _at_(negedge clk) in an always
  block

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Continuous Assignment(1/2)

• Used for datapath descriptions
• Used to model combinational circuits

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Continuous Assignment(2/2)

• Avoid logic loop
• Without disabling the combinational feedback
  loop, the static timing analyzer cant resolve

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Compare (????)

• Unsupport compare X and Z
• X and Z maybe make circuit occur exception
• Dont coding X or Z in RTL code(except casez
  or casex)
• Comparisons to an X or Z are always ignored.
• Comparison is always evaluated to false,which may
  cause simulation synthesis mismatch.

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For Loop

• Provide a shorthand way of writing a series of
  statements.
• Loop index variables must be integer type.
• Step, start end value must be constant.
• In synthesis, for loops loops are unrolled,
  and then synthesized.

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Finite State Machine

• Contain only one type of sequential element
• Contain only one reset signal
• Separate combinational (next_state) sequential
  block(current_state)
• Symbolic state names - easy to identify and
  modify
• Make state assignments using parameters with
• symbolic state names

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Explicit Finite State Machine

• Use explicit FSM to describe asynchronous reset
  FSM
• Use if or case statement to allow compact
  description of state machine logic

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Synopsys HDL Compiler Directive

• //synopsys translate_on //synopsys
  translate_off control the HDL Compiler
  translation of Verilog code off on

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Use Parentheses Properly

• out ((a(bc))de)f

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Resource Allocation
Without resource allocation

• if A 1 then
• E B C
• else
• E B D
• end

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Resource Allocation

• if A 1 then
• temp C // A temporary variable introduced.
• else
• temp D
• end if
• E B temp

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Avoid delay times glue logic

• Do not use any delay constant in RTL code
• Always _at_(posedge clock)
• Temp_a lt 2 temp_b
• Top module dont contain logic (function) between
  module and other module

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Avoid snake path

• ??????????, ?????????????????

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Setting Wire Load
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Setting Wire Load Model

• Wire load model estimates wire capacitance based
  on chip area cell fanout.
• Setting this information during compile in order
  to model the design more accurately .

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Design Ware Library

• DesignWare is technology-independent soft
  macros such as adders, comparators, etc., which
  can be synthesized into gates from your target
  library

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Design Ware Library

• Invoke Design Ware component with 2 ways
• Inference let design compiler to choose the
  DesignWare component according to the constraints
• Instantiation explicitly instantiate synthesis
  modules

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Design Ware Library
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Design Ware Library
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Design Ware Library
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Multiple Design Instance

• Use dont_touch, ungroup, uniquify to fix it.
• The easiest way is uniquify, but needs much
  memory compile time.
• If you want to preserve the hierarchy source
  sharing, use dont_touch.
• If you want your design to have the BEST result,
  recommend to use ungroup. But it needs the most
  memory and compile time.

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Uniquify
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Floating Port Removing

• Due to some ports in the standard cells are not
  used in your design
• remove_unconnected_ports -blast_buses get_cells
  -hierarchical

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structure

• The default logic-level optimization
  strategysuitable for structured circuits (e.g.
  adders and ALUs)
• set_structure lttrue falsegt
• -design ltlist of designsgt
• -boolean ltlow medium highgt
• -timing lttrue falsegt

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Flatten

• Flatten is default OFF
• Remove all intermediate variable
• Result a two-level sum-of-product form
• Use when you have a timing goal and have dont
  cares(x) in your HDL code
• set_flatten lttrue falsegt
• -design ltlist of designsgt
• -effort ltlow medium highgt
• -phase lttrue falsegt

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Input delay Model
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Setting input dalay
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Output Delay Model

• Clock-cycle gt DFFclk-Qdelay d e DFFsetup
• Output delay e DFFsetup

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Setting Output Delay
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Combination Circuit Maximum Delay Constraints

• For combinational circuits primarily (i.e. design
  with no clock)
• Select the start end points of the timing path
• Attributes/Optimization Constraints/Timing
  Constraints

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Combination Circuit Maximum Delay Constraints
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Analyze Elaborate

• Analyze and Elaborate
• Use Analyze and Elaborate to read HDL designs
  and convert them to Synopsys database format
• Read
• Use Read (read_file is the command-line
  equivalent) to read designs that are already in
  format

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Sequential Circuit - Specify Clock

• create_clock -name "A" -period B -waveform C D
  E
• A ?? clock name
• B ?? ????,ex. 10 (ns)
• C ?? rising edge ex. 0
• D ?? failling edge,ex.????/2 5 (ns)
• E ?? your module clock pin name
• set_dont_touch_network find clock A
• Dont add any buffer in clock network
• set_fix_hold find clock A

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Clock Tree Modeling Example
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Setting Area Constraint

• Attributes gt Optimization Constraints gt Design
  Constraints

??0, Tool??????????
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Compile Boundary Optimization
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Compile - map_effort

• Compile design with default effort level (medium)
  for best results
• Compile design with map effort high it does
  critical path re-synthesis but it will use more
  CPU time in some cases the action of compile
  will not terminate
• compile -map_effort high

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Compile

• Top Level compiles only the top level of the
  design, leaving the rest uncompiled
• Ungroup All Ungroups the entire hierarchy so
  that all logic is compiled as one module
• Auto Ungroup when enabled, you may choose
  either area or delay as the trigger, and the
  synthesizer will automatically ungroup designs to
  meet constraints if the
• constraints are not being met

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Check Design

• Performing a design check can find
  inconsistencies in your design that may or may
  not be problems.

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Change Naming Rule

• ????,?command window??????

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Change Naming Rule
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Fix Multiple Port Net

• if there is any assignment problem, choose the
  block use the dc_shell command as follow to fix
  it
• set_fix_multiple_port_nets -all -buffer_constants
• compile -map_effort medium

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Basic Command

• ?????read (bottom up)
• ?? read -format ???? ????
• ???? ????verilog
• Ex
• read -format verilog ALU.v

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Basic Command

• ??????current_design
• ?? current_design ????
• current_design get_designs ????
• Ex current_design ALU
• ???????link
• ?? link

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Basic Command

• ungroup flatten all
• set_dont_use typical/CLK (????? CLK ???????)
• set_dont_use slow/CLK
• compile -map medium -area medium
  boundary_optimization
• report_area gt Report_area.txt
• report_timing -significant_digits 4 gt
  Report_timing.txt
• report_power gt Report_power.txt

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Basic Command

• write -format verilog -hierarchy -output gate.v
  
• (?? gatelevel code), gatelevel simulation ???
• write_sdf -version 1.0 "./report/gate.sdf
• (Write Stand Delay Format), gatelevel
  simulation ???
• write_sdc -version 1.7 "./report/gate.sdc
• To write out a script in Synopsys Design
  constraints format (SDC) to a file that can be
  used later for the place and route tools

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Gatelevel - Simulation
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Gate-Level Simulation

• Add the Verilog model gate-level netlist
• Add Verilog model of standard cell (temc13.v)
• Modifiy your testfixture file
• sdf_annotate("the_SDF_file_name",the_top_level_mo
  dule _instance_name)
• For example sdf_annotate("chip.sdf", top)

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Gate-Level Simulation

• ??????testbench??initial block
• sdf_annotate(gate.sdf,DWT)//?????? Delay
  Information
• dumpvars
• dumpfile(DWT_Power.vcd) //?? prime power
  ??????