Input-output and Communication

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Input-output and Communication
Lecture 23

• Prof. Sin-Min Lee
• Department of Computer Science

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Two mechanisms to support communication between
OS and hardware Interrupts and
exceptions Device Interrupt hardware -gt
OS Device Registers OS -gt hardware Each device
is assigned an interrupt number (for errors,
completed tasks) sets a bit in controller,
causes CPU to stop
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Interrupt
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The memory address in the above table (column 3)
is the location of the handler routine that will
be executed as a result of the interrupt. Location
of table hardwired in machine, initialized by OS
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• Direct-memory access
• Often used for block access devices that move
  large chunks of data, e.g., disk, graphics device
  
• I/O Device has smarts built into its controller. 
  The DMA hardware allows device to directly read
  and write memory without processor intervention.
• The processor sets up the DMA device controller
• What operation to perform
• What locations on the I/O device to access (in
  the case of a disk access, the track and cylinder
  of data block)
• What locations in memory to access
• When done, the DMA device will interrupt the
  processor
• A status register indicates the status of the
  request once completed or terminated

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• DMA causes havoc with caches
• Can invalidate cache lines that are involved
• Can update the cache
• Possibly flush cache whenever DMA occurs
• DMA and virtual memory
• DMA device could use Physical address of where in
  memory to place/read data, but the transfer must
  then be broken into frame sized chunks.
• DMA device could use Virtual address of where in
  memory to place/read data, but then it requires
  the physical mappings of each page to send.
•  

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I/O Interfaces - Example of I/O Interface

• Control register

• Receives control information from CPU
• A bit in this register determine the operating
  mode of the device

• Status register

• Contains bit to indicate status condition and
  record any error during transfer

• Interface registers

• Communicate with CPU via bidirectional bus

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I/O Interfaces - Example of I/O Interface

• Data bus select the interface units through chip
  select input (CS) and two register select (RS0)
  and (RS1)
• CPU and I/O devices are likely to have different
  clock rate that are not synchronized
• A control signal is needed to
• Indicate time the data is being transmitted
• Indicate the window of time when the address is
  valid

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I/O Interfaces - Example of I/O Interface

• Two methods to perform this timing between CPU
  and devices
• Strobing
• Handshaking

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I/O Interfaces - Strobing
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I/O Interfaces - Handshaking