Hamming Code

1
Hamming Code

• Clarissa David
• Timmy Lau
• WingChing Lin
• Jonathan Lee
• Advisor Dr. David Parent
• December 7, 2005

2
Agenda

• Abstract
• Introduction
• Why a Hamming Code?
• Potential Applications
• Theory of Operation
• Calculations
• Cadence Details
• Summary of Results
• Cost Analysis
• Conclusions

3
Abstract

• Target Specification
• Clock Frequency 200MHz
• Load Capacitance 30fF
• Area 900x500 micron squared
• Actual Specification
• Clock Frequency 160MHz
• Load Capacitance 30fF
• Area 932.55 x 915.45 micron squared

4
Introduction

• Hamming Code
• Detects single and double-bit errors
• Application
• Telecommunication (i.e. networking)
• Theory
• Using 4 data bits, can generate 3 correction bits
  giving a total of 7 bits
• Can correct any single bit error

5
Longest Path
CELL BIT WN Load (cm) WP Load (cm) CgCint tphl (s) WN (cm) WP (cm)
NAND2A 1     3.0000E-14 2.00E-10 3.80E-04 3.38E-04
NAND2B 2 3.80E-04 3.38E-04 1.2053E-14 1.90E-10 2.22E-04 1.98E-04
INVA 3 2.22E-04 1.98E-04 7.0588E-15 7.50E-11 1.53E-04 2.77E-04
INVB 4 1.53E-04 2.77E-04 7.2093E-15 7.50E-11 1.55E-04 2.81E-04
NAND3A 5 1.55E-04 2.81E-04 7.3253E-15 2.30E-10 3.02E-04 1.78E-04
INVC 6 3.02E-04 1.78E-04 8.0627E-15 8.00E-11 1.52E-04 2.75E-04
INVD 7 1.52E-04 2.75E-04 7.1669E-15 7.50E-11 1.55E-04 2.80E-04
NAND2C 8 1.55E-04 2.80E-04 7.2926E-15 1.20E-10 4.36E-04 3.92E-04
INVE 9 4.36E-04 3.92E-04 1.3902E-14 9.50E-11 1.82E-04 3.28E-04
NAND4A 10 1.82E-04 3.28E-04 8.5568E-15 3.40E-10 3.15E-04 1.50E-04
NAND4B 11 3.15E-04 1.50E-04 7.8037E-15 3.40E-10 3.00E-04 1.50E-04
INVF 12 3.00E-04 1.50E-04 7.5520E-15 7.50E-11 1.61E-04 2.91E-04
NAND2D 13 1.61E-04 2.91E-04 7.5893E-15 1.50E-10 2.50E-04 2.24E-04
NAND2E 14 2.50E-04 2.24E-04 7.9558E-15 1.50E-10 2.50E-04 2.24E-04
INVG 15 2.50E-04 2.24E-04 7.9558E-15 7.50E-11 1.67E-04 3.03E-04
NAND4C 16 1.67E-04 3.03E-04 7.9005E-15 3.40E-10 2.85E-04 1.50E-04
NAND3B 17 2.85E-04 1.50E-04 7.3002E-15 2.10E-10 3.00E-04 1.78E-04
INVH 18 3.00E-04 1.78E-04 8.0177E-15 7.50E-11 1.68E-04 3.05E-04
6
Schematic
Note This is an Error Generator
Gate Level Schematic of Hamming Code
7
Schematic
Block schematic of Hamming without the flip-flop
8
Schematic
Schematic of Hamming Code with flip-flop at the
start
9
Layout
Layout of Hamming Code
10
Verification DRC
Verification of DRC Passing
11
Verification LVS
Verification of LVS PASSED!!!!
12
Simulation
NCVerilog of Hamming Code Logic
13
Simulation
14
Simulation
Simulation of Hamming Code with flip-flop
15
Simulation
Simulation of error generator
16
Cost Analysis
Cost Analysis Cost Analysis
Task Length of Time
Verifying Logic 1 Day
Verifying Timing 1 Day
Layout 7 Days
Post Extracted Timing 1 Day
TOTAL TIME 10 Days
But from us.. FREE!!!!!
17
Lessons Learned

• EXPOSE YOURSELF TO THE PROJECT EARLY
• Be organized about your routing
• Debugging layout
• Work together as a team
• EXPOSE YOURSELF TO THE PROJECT EARLY !!!

18
Summary

• Complete Circuit
• Clock Frequency 160MHz
• Area 932.55 x 915.45 microns squared
• Load Capacitance 30fF

19
Acknowledgements

• Thanks to Cadence Design Systems
• Thanks to Professor David Parent
• Thanks to the current and past students of EE166