Computer Architecture Lecture 4 17th May, 2006

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Computer ArchitectureLecture 417th May, 2006

• Abhinav Agarwal
• Veeramani V.

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Recap

• Simple Pipeline hazards and solution
• Data hazards
• Static compiler techniques load delay slot,
  etc.
• Hardware solutions Data forwarding,
  out-of-order execution, register renaming
• Control hazards
• Static compiler techniques
• Hardware speculation through branch predictors
• Structural hazards
• Increase hardware resources
• Superscalar out-of-order execution
• Memory organisation

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Memory Organization in processors

• Caches inside the chip
• Faster Closer
• SRAM cells
• They contain recently-used data
• They contain data in blocks

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Rational behind caches

• Principle of spatial locality
• Principle of temporal locality
• Replacement policy (LRU, LFU, etc.)
• Principle of inclusivity

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Outline

• Instruction Level Parallelism
• Thread-level Parallelism
• Fine-Grain multithreading
• Simultaneous multithreading
• Sharable resources Non-sharable resources
• Chip Multiprocessor
• Some design issues

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Instruction Level Parallelism

• Overlap execution of many instructions
• ILP techniques try to reduce data and control
  dependencies
• Issue out-of-order independent instructions

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Thread Level Parallelism

• Two different threads have more independent
  instructions
• Better utilization of functional units
• Multi-thread performance is improved drastically

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A simple pipeline
source EV8 DEC Alpha Processor, (c) Intel
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Superscalar pipeline
source EV8 DEC Alpha Processor, (c) Intel
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Speculative execution
source EV8 DEC Alpha Processor, (c) Intel
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Fine Grained Multithreading
source EV8 DEC Alpha Processor, (c) Intel
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Simultaneous Multithreading
source EV8 DEC Alpha Processor, (c) Intel
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Out of Order Execution
source EV8 DEC Alpha Processor, (c) Intel
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SMT pipeline
source EV8 DEC Alpha Processor, (c) Intel
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Resources Replication required

• Program counters
• Register maps

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Replication not required

• Register file (rename space)
• Instruction queue
• Branch predictor
• First and second level caches etc.

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Chip multiprocessor

• Number of transistors going up
• Have more than one core on the chip
• These still share the caches

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Some design issues

• Trade-off in choosing the cache size
• Power and performance
• Super pipelining trade-off
• Higher clock frequency and speculation penalty
  Power
• Power consumption

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Novel techniques for power

• Clock gating
• Run non-critical elements at a slower clock
• Reduce voltage swings (Voltage of operation)
• Sleep Mode/ Standby Mode
• Dynamic Voltage Frequency scaling