Comparing the SHARC and HAMMERHEAD DSPs

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Comparing the SHARC and HAMMERHEAD DSPs

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• Prepared by
• Eugene So

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To be tackled today

• Comparison of Processor Architectures
• ADSP2106X (SHARC)
• ADSP2116X (HAMMERHEAD)
• Focus on the advantages of the Hammerhead
• SIMD Engine
• Benchmark
• CRISP requirements

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SHARC Architecture
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Hammerhead Architecture
32-bit PMA bus (vs 24-bit)
48/64-bit PMD bus (vs 48-bit)
40/64-bit DMD bus (vs 40-bit)
Dual processor, Shared memory
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Single Instruction Multiple Data Engine

• The Hammerhead is a SHARC with two CPUs
• The same instruction is executed in both CPUs,
  but each CPU operates on different data
• CPU1 can be controlled
• CPU2 simply performs the same operation as CPU1
  on the next memory location.
• This is called a Single Instruction Multiple Data
  (SIMD) Engine

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Advantages of SIMD

• Double cycle performance
• If an algorithm can be broken into 2 components
  then CPU1 can process memory elements 1, 3, 5, 7
  etc., and CPU2 can process 2, 4, 6, 8 etc.
• Examples
• FIR, divide, inverse square root, matrix multiply

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FIR example

• y(n) summation from k0 to M of h(k) x(n-k)
• / HAMMER HEAD CODE SEGMENT ... /
• lcntrsamples, do macs until lce / FIR loop /
• macs f12f0f4, f8f8f12, f0dm(sample_pt,m3),
  f4pm(coeff_pt,m9)
• / (2 samples) (2 coeffs), accum, read 2
  samples, read 2 coeffs /
• Cycle count
• Hammerhead TAPS/2 16
• SHARC TAPS 9

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Advantages of SIMD (cont.)

• Double Bandwidth
• Accessing two memory locations in a single
  instruction essentially doubles the bandwidth
  between memory and the CPUs
• Special Addressing Modes
• The data busses are widened to 64-bits on the
  Hammerhead to accommodate SIMD
• One addressing mode on the Hammerhead allows
  identical data to be copied into both register
  files
• Another allows 64-bit data to be split between
  the two register files

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Advantages of SIMD (cont.)

• Complex Arithmetic Handling
• CPU1 handles real component
• CPU2 handles imaginary component

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Complex Vector Add example

• z(n) x(n) jy(n)
• / HAMMERHEAD CODE SEGMENT /
• include "def21160.h" / Symbol Definition
  File /
• .global cx_vec_add
• / program memory code /
• .section/pm seg_pmco
• cx_vec_add
• bit set MODE1 PEYEN / SIMD enabled /
• lcntrsamples, do add until lce
• f0dm(i0,m0), f4pm(i8,m8) / f0 Xr, s0
  Xi, f4 Yr, s4 Yi /
• add f8f0f4, dm(i1,m0)f8 / f8 Xr Yr, s8
  Xi Yi, store result /
• rts (db)

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Benchmark
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CRISP Requirements
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Conclusion

• The Hammerhead is a SHARC with two CPUs
• Two heads are (usually) better than one! But
  also more costly!