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Seminar: Moderne Methoden der analogen Schaltungstechnik

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Seminar: Moderne Methoden der analogen Schaltungstechnik. Teil III: Rein Digital-PLL, ... In the linear region (analog mode) ?C/?V is very steep KVCO=?f/?V is high. ... – PowerPoint PPT presentation

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Title: Seminar: Moderne Methoden der analogen Schaltungstechnik


1
Seminar Moderne Methoden der analogen
Schaltungstechnik
  • Teil III Rein Digital-PLL,
  • Rein Digital-Sender
  • Eugenio Di Gioia

2
Part I
  • Digitally Controlled Oscillator

3
1. Digitally Controlled Oscillator (DCO) with
LC-Tank 7
(a) VCO, (b) DCO
4
C-V Curve, Example PMOS-Varactor
  • VCO The varactors work in the linear region
  • DCO The varactors work in the
    inversion/depletion regions (on/off)

5
C-V Curve, Example PMOS-varactor
  • In the linear region (analog mode) ?C/?V is very
    steep ? KVCO?f/?V is high. The oscillator is
    extremely sensible to all sorts of disturbances
    on VG or to variation on VDD (frequency pushing)
  • In the inversion/depletion regions (digital
    mode) KVCO ?f/?V 0, that means low
    sensitivity to power supply/tuning voltage noise

6
DCO 7 measurement results (Bluetooth compatible)
7
DCO 7 frequency locking
  • Frequency locking is performed in four steps
  • First step coarse calibration, an 8-bit word
    controls 8 large binary-weighted capacitors
    (2.316 MHz steps, frequency range 592 MHz)
  • Second step channel acquisition, an 8-bit word
    controls 8 medium-sized binary-weighted
    capacitors (461 KHz steps, frequency range 118
    MHz)

8
DCO 7 frequency locking
  • Third step tracking, a 64-bit word (thermometer
    encoded) controls 64 small unit-weighted
    (identical dimensions) capacitors (23 KHz steps,
    frequency range 1.472 MHz)
  • Fourth step, together with the third one
    fractional tracking, a 5-bit word is S?-modulated
    into a high-rate 3-bit word (8 levels).
    Quantization noise is shaped and filtered through
    circuit parasitic capacitances. The effective
    frequency resolution is 23 KHz /25 718 Hz
  • Unity-weighting guarantees monotonicity. DEM
    technique can be used to improve matching

9
DCO Scheme
  • I/O Fully Digital
  • N-Bit Control Word
  • The Gain KDCO ?f/LSB sets the frequency
    resolution
  • The effective resolution can be improved by
    using a S?-modulated control word
  • To avoid spurious tones a high-order S? is
    required

10
S-domain model of a classic PLL
11
z-domain model of the ADPLL 9
N determines the ratio fV/fREF and is generated
through the Frequency Control Word (FCW)
12
ADPLL 9
  • fV is obtained accumulating the number of rising
    edge transitions of the DCO-Output (fV)
  • fREF is obtained accumulating the Frequency
    Control Word (FCW) with the rising edge
    transitions of the retimed fREF (see below)
  • fREF 13 MHz, fV 2.4 GHz -gt fREF and fV are
    sampled values with different frequencies
    metastability problems
  • To achieve the same sampling rate fREF is
    oversampled at the frequency fV. Now we can
    perform the phase comparison between synchronous
    signals

13
ADPLL 9
Retimed FREF
fV
The retimed fREF has a frequency-rate of 13 MHz
and it is synchronized with fV
fV
Retimed FREF
14
Retiming of fREF 9
A quantization error 0lteltTV results after the
synchronization of NfREF with fV. This causes an
error in the phase estimation, that limits the
phase resolution
15
Time-to-digital converter (TDC) 6, 8
  • Solution fractional error correction based on a
    TDC
  • The TDC measures the time difference e between a
    reference rising edge and the next DCO rising
    edge (see previous slide)
  • Its resolution is a single inverter delay (about
    20 ps)

16
Time-to-digital converter (TDC) 6, 8
  • The DCO-Output Clock is fed to a chain of 24
    CMOS-Inverter
  • The reference clock samples the outputs of the
    inverters by means of 24 Latches
  • Every 1 in the output word means a delay of
    ?tINV
  • The Pseudo-Thermometer Word is converted to
    binary-coded, normalized to the DCO-clock period
    (a fractional number between 0 and 1 is obtained)
  • The output is then subtracted at the input of the
    Phase-Detector (a simple subtractor)

Normalizing factor
17
Digital Phase-Detector model
18
Part II
  • All-Digital Transmitter

19
All-Digital Transmitter
  • Based on an all-digital phase-locked loop (ADPLL)
  • The hearth of the system is a DCO
  • A Digitally-controlled Power Amplifier (DPA) is
    used

20
Signal Modulation
  • Frequency and amplitude modulations are
    implemented in two separate paths (polar
    architecture)
  • Signal Frequency Modulation performed by the
    ADPLL
  • Signal Amplitude Modulation performed by the DPA
  • Modulation algorithm
  • The Cartesian coordinates (x,y) of the digital
    samples are converted into polar coordinates
    (f,A)
  • The phase f is differentiated to obtain the
    frequency deviation ?f ?f/?t
  • The Amplitude information word (NA bits) is
    S?-modulated and fed to the DPA
  • The Frequency information word (NF bits) is
    S?-modulated and fed to the ADPLL

21
Digitally controlled Power Amplifier (DPA)
  • A digital word sets the RF-Amplitude through
    NMOS switches fine amplitude resolution is
    achieved through S?-Dithering of the control word
  • The Power Amplifier is Off-Chip
  • A matching network filters higher harmonics of
    the digital carrier

22
Digitally controlled Power Amplifier (DPA)
  • The DPA is controlled by the PM digital carrier
    of the ADPLL and by the S?-modulated amplitude
    word
  • The matching network is chosen so that the drain
    voltage of the MOS transistors is low when the
    output current is high and vice versa
  • The DPA operates as a near class-E amplifier
  • The Output signal of the DPA after the matching
    network is in the form

23
References
  • 1 R. G. Vaughan et al. The theory of bandpass
    sampling, IEEE 1991
  • 2 S. Lindfors et al. A 3-V 230-MHz CMOS
    Decimation Subsampler, IEEE 2003
  • 3 D. Jakonis et al. A 2.4-GHz RF Sampling
    Receiver Front-End in 0.18 µm CMOS, IEEE 2005
  • 4 D. Jakonis et al. A 1 GHz Linearized CMOS
    Track-and-Hold Circuit, IEEE 2002
  • 5 B. Razavi, Principles of Data Conversion
    System Design, IEEE Press, 1995
  • 6 R. B. Staszewski et al. All-Digital TX
    Frequency Synthesizer and Discrete-Time RX for
    Bluetooth Radio in 130-nm CMOS, IEEE 2004
  • 7 R. B. Staszewski et al. A first
    multigigahertz Digitally Controlled Oscillator
    for wireless applications, IEEE 2003
  • 8 R. B. Staszewski et al. All-Digital PLL and
    Transmitter for Mobile Phones, IEEE 2005
  • 9 R. B. Staszewski et al. Phase-Domain
    All-Digital Phase-Locked Loop, IEEE 2005
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